[U-Boot] [RFC 0/5] powerpc: Add support 2 stage boot loader for corenet platform

[MJ embd]

Trivial Question, Which part of the SPL code uses HEAP?

On 9/16/13, Prabhakar Kushwaha <prabhakar at freescale.com> wrote:
>
> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
> ---
>
> Add support of 2 stage NAND boot loader in cornet platforms using SPL
> framework.
> This will be helpful for those SoC which has less internal SRAM(128K).
>
> here, PBL initialise the internal SRAM and copy SPL(96K) in SRAM.
> SPL further initialise DDR using SPD and environment variables and copy
> u-boot(512 KB) from NAND flash to DDR.
> Finally SPL transer control to u-boot for futher booting.
>
> SPL has following features:
>  - Executes within 128K
>  - SPL size 96K
>  - No relocation required
>
>  Run time view of SPL framework
>  ==============================
>  -----------------------------------------------
>  Area        | Address                         |
>  -----------------------------------------------
>  GD, BD      | 0xFFFE0000 (1K)                 |
>  -----------------------------------------------
>  HEAP        | 0xFFFE0400 (26K) grow downwards |
>  -----------------------------------------------
>  STACK       | 0xFFFE8000 (5K)  grow upwards   |
>  -----------------------------------------------
>  U-boot SPL  | 0xfffe8000 – 0xfffffffc (96K)   |
>  -----------------------------------------------
>
> 96K + 5K + 26K + 1K = 128K
> ---
>  This patch set contains:-
>
>  [RFC 1/5] powerpc:Add support of SPL non-relocation
>
>  [RFC 2/5] powerpc/SPL:Allow Parsing of LAW table in both SPL & non SPL
>
>  [RFC 3/5] common/env: Point default envirenoment for GD
>
>  [RFC 4/5] SPL:Defines function required to env read for IFC & env_nand
>
>  [RFC 5/5] B4860QDS: Add support of 2 stage NAND boot loader
> --
> 1.7.9.5
>
>
>


-- 
-mj