[U-Boot] Xilinx Zed Board resets with Master

[Michal Simek]

On 04/03/2014 11:27 AM, Tim Sander wrote:
> Hi
>>> On 03/27/2014 05:32 PM, Tim Sander wrote:
>>>> Hi Michal
>>>>
>>>> Am Donnerstag, 27. März 2014, 14:17:41 schrieb Michal Simek:
>>>>>>>>> Please check and may be you can try u-boot-dtb.elf.
>>>>>>>>
>>>>>>>> Mh,  don't know how to create this kind of file?
>>>>>>>
>>>>>>> Jagan maybe knows more but I don't think u-boot-dtb.elf is generated.
>>>>>>> Just u-boot-dtb.bin is generated which should be copied as data file
>>>>>>> in xmd and not sure if binary file can be directly used for bootgen.
>>>>
>>>> If adding the dtb file in the boot.bif file is not the right way and no
>>>> elf file with dtb is generated: What is the right way to generate an
>>>> image for use with the SD-Card?
>>>
>>> you can just use static u-boot configuration.
>>
>> I assume you mean static configuration a config with OF_CONTROL disabled.
>> Ok, i have tried to boot that with bootgen. That does not work.
>> Loading that into memory and booting it from within the debugger works
>> though. In both cases with or without OF_CONTROL enabled.
>>
>>> I have never tried to add dtb as partition to boot.bin.
>>> If you want to use this dtb driver u-boot I would suggest you
>>> to look at u-boot SPL which should be able to handle binary formats
>>> with dtbs.
>>
>> So my main focus is to test CONFIG_ARMV7_NONSEC to boot linux in
>> normal mode. I wanted to test recent mainline with that. So focusing on
>> u-boot SPL is to far off my targets. So i am happy with hardware debugger
>> loadeing for the time beeing.
>>
>> Getting back to CONFIG_ARMV7_NONSEC. This is unfortunatly not working with
>> the Zynq.  Currently the board switches to monitor mode but when the u-boot
>> switches to normal mode it jumps to PC:0xc  (LR:0x10) which seems like a
>> data abort exeption or some other secure mode violation exception?
>> Is there a good way to find out what happened? I am currently stuck with
>> this and my local FAE has also no idea. Attached is a patch which at least
>> works until the return from the monitor mode.
> Just a small information: I can boot a OF_CONTROL on a RevC Zynq 
> Board but not Rev. D. So i can at least confirm that a board with RevC boots a 
> mainline u-boot with OF_CONTROL disabled. I have no idea why the bootgen for 
> the Rev. D board fails even if i have replaced the bitstream for the non eng. 
> sample FPGA. But at least that also works when loaded with an HW-Debugger.

Interesting. Please use xilinx forums then can help you.

M