[U-Boot] [PATCH 08/10][v2] Makefile: Add support of CONFIG_SPL_FSL_PBL

[Prabhakar Kushwaha]

Objective of this target to have concatenate binary having
 - SPL binary in PBL command format
 - U-boot binary

Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
---
 Changes for v2:
  - rename CONFIG_RAMBOOT_PBLSPL to CONFIG_SPL_FSL_PBL

 Makefile |   19 +++++++++++++++++++
 README   |    4 ++++
 2 files changed, 23 insertions(+)

diff --git a/Makefile b/Makefile
index 25cbc95..99533a5 100644
--- a/Makefile
+++ b/Makefile
@@ -699,7 +699,11 @@ ALL-y += u-boot.srec u-boot.bin System.map
 
 ALL-$(CONFIG_NAND_U_BOOT) += u-boot-nand.bin
 ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin
+ifeq ($(CONFIG_SPL_FSL_PBL),y)
+ALL-$(CONFIG_RAMBOOT_PBL) += u-boot-with-spl-pbl.bin
+else
 ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl
+endif
 ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin
 ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img
 ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin
@@ -882,6 +886,21 @@ endif
 u-boot-img.bin: spl/u-boot-spl.bin u-boot.img FORCE
 	$(call if_changed,cat)
 
+#Add a target to create boot binary having SPL binary in PBI format
+#concatenated with u-boot binary. It is need by PowerPC SoC having
+#internal SRAM <= 512KB.
+MKIMAGEFLAGS_u-boot-spl.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
+		-R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage
+
+spl/u-boot-spl.pbl: spl/u-boot-spl.bin FORCE
+	$(call if_changed,mkimage)
+
+OBJCOPYFLAGS_u-boot-with-spl-pbl.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \
+			  --gap-fill=0xff
+
+u-boot-with-spl-pbl.bin: spl/u-boot-spl.pbl u-boot.bin FORCE
+	$(call if_changed,pad_cat)
+
 # PPC4xx needs the SPL at the end of the image, since the reset vector
 # is located at 0xfffffffc. So we can't use the "u-boot-img.bin" target
 # and need to introduce a new build target with the full blown U-Boot
diff --git a/README b/README
index a66afb1..68b38f6 100644
--- a/README
+++ b/README
@@ -486,6 +486,10 @@ The following options need to be configured:
 		PBI commands can be used to configure SoC before it starts the execution.
 		Please refer doc/README.pblimage for more details
 
+		CONFIG_SPL_FSL_PBL
+		It adds a target to create boot binary having SPL binary in PBI format
+		concatenated with u-boot binary.
+
 		CONFIG_SYS_FSL_DDR_BE
 		Defines the DDR controller register space as Big Endian
 
-- 
1.7.9.5