[U-Boot] [PATCH 07/11] MX6: use macro building for MX6Q/MX6DL iomux regs

[Nikita Kiryanov]

On 04/09/2014 06:46 PM, Tim Harvey wrote:
> On Wed, Apr 9, 2014 at 7:57 AM, Nikita Kiryanov <nikita at compulab.co.il> wrote:
>> Hi Tim,
>>
>>
>> On 04/03/2014 09:01 AM, Tim Harvey wrote:
>>>
>>> This is an attempt at using a macro to allow mx6dl-ddr.h and
>>> mx6q-ddr.h registers to be used together which is needed for an SPL
>>> bootloader
>>> that can run on either CPU's and must configure MMDC iomux dynamically.
>>>
>>> I am trying to come up with a solution similar to Eric's approach with the
>>> similar issue regarding IMX pinmux but this approach is broken in that
>>> imximage
>>> will choke on the cfgtmp file due to the fact that the pre-processor won't
>>> use the enum's as it did the #defines. I'm looking for some positive
>>> suggestions here or perhaps someone else can come up with a solution for
>>> this
>>> particular issue which I haven't been able to resolve.
>>
>>
>> Why can't you just rename the register name #defines without enclosing
>> them in an anonymous enum? Then they could coexist and will be usable
>> by imximage.
>>
>> --
>> Regards,
>> Nikita.
>
> Nikita,
>
> The cfg files are currently all written to use the IOMUX register
> names as MX6_ (no Q vs DL)  so that a single cfg file can be used for a
> build-time configuration of IMX6Q or IMX6DL.

OK now I understand. It seems to me that you only have this problem
because you are using these address #defines as values for
mx6_mmdc_ioregs structs to define a register mapping. You can
also define this mapping by using a struct template that matches the
register layout and a base address, both of which change between CPU
types.

You can find an example of this in the Wandboard SPL implementation.
It's not in mainline ATM so you'll have to download their BSP.
The template + base addr method also doesn't use up additional memory
to define this layout, which is a point in its favor.

>
> Regards,
>
> Tim
>


-- 
Regards,
Nikita.