[U-Boot] [PATCH v4 00/10] ARMv7: add PSCI support to U-Boot
Dennis Gilmore
dennis at ausil.us
Sat Apr 26 16:24:31 CEST 2014
On Sat, 26 Apr 2014 13:17:01 +0100
Marc Zyngier <marc.zyngier at arm.com> wrote:
> PSCI is an ARM standard that provides a generic interface that
> supervisory software can use to manage power in the following
> situations:
> - Core idle management
> - CPU hotplug
> - big.LITTLE migration models
> - System shutdown and reset
>
> It basically allows the kernel to offload these tasks to the firmware,
> and rely on common kernel side code that just calls into PSCI.
>
> More importantly, it gives a way to ensure that CPUs enter the kernel
> at the appropriate exception level (ie HYP mode, to allow the use of
> the virtualization extensions), even across events like CPUs being
> powered off/on or suspended.
>
> The main idea here is to turn some of the existing U-Boot code into a
> separate section that can live in secure RAM (or a reserved page of
> memory), containing a secure monitor that will implement the PSCI
> operations. This code will still be alive when U-Boot is long gone,
> hence the need for a piece of memory that will not be touched by the
> OS.
>
> This patch series contains 3 parts:
> - the first four patches are just bug fixes
> - the next two refactor the HYP/non-secure code to allow relocation
> in secure memory
> - the last four contain the generic PSCI code and DT infrastructure
>
> This implements the original 0.1 spec, as nobody implements the new
> 0.2 version so far. I plan to update this support to 0.2 once there is
> an official binding available (and support in the kernel).
>
> Most of the development has been done on an Allwinner A20 SoC, which
> is the main user of this code at the moment. I hope new SoCs will be
> using this method in the future (my primary goal for this series being
> to avoid more stupid SMP code from creeping up in the Linux
> kernel). As instructed, I've removed the A20 support code and made it
> a separate series, as there is now an effort to mainline this code
> (see Ian Campbell patch series).
>
> With these three series applied, the A20 now boots in HYP mode, Linux
> finds the secondary CPU without any SMP code present in the kernel,
> and runs KVM out of the box. The Xen/ARM guys managed to do the same
> fairly easily, as did at least one XVizor user.
>
> This code has also been tested on a VExpress TC2, running KVM with all
> 5 CPUs, in order to make sure there was no obvious regression.
>
> The code is also available at:
> git://git.kernel.org/pub/scm/linux/kernel/git/maz/u-boot.git
> wip/psci-v4
>
> A fully merged branch with the A20 support is in the wip/psci-v4-a20
> branch of the same repo.
>
> Cheers,
>
> M.
>
> From v3:
> - Return ARM_PSCI_RET_INVAL instead of ARM_PSCI_RET_NI when PSCI is
> entered with an invalid function code.
> - Fix !NONSEC compilation
> - Rebased on top of adcdeac
>
> From v2:
> - Dropped the secure stack allocation from the generic PSCI code.
> There was too little space there for it to be really useful, and the
> arch code knows a lot better about its requirements anyway. It is now
> the responsibility of the arch code to provide a stack. This allows
> it to get rid of the silly game with the thread registers that was
> confusing everyone...
> - Added provision for FIQ handling in secure mode. Allwinner A20 is
> going to require this for CPU_OFF.
> - Better integration of the FDT injection code with the rest of the
> code, fixing the truncated FDT issue that people have been reporting
> (courtesy of Ma Haijun).
> - Cleanup of the AW-specific code (stack allocation, timer macro).
> - Rebased on mainline U-Boot (on top of 22a240c32c13).
>
> From v1:
> - Complete rewrite, now directly relocating the secure code withing
> U-Boot, instead of having a separate psci blob.
>
> Ma Haijun (1):
> ARM: convert arch_fixup_memory_node to a generic FDT fixup function
>
> Marc Zyngier (9):
> ARM: HYP/non-sec: move switch to non-sec to the last boot phase
> ARM: HYP/non-sec: add a barrier after setting SCR.NS==1
> ARM: non-sec: reset CNTVOFF to zero
> ARM: add missing HYP mode constant
> ARM: HYP/non-sec: add separate section for secure code
> ARM: HYP/non-sec: allow relocation to secure RAM
> ARM: HYP/non-sec: add generic ARMv7 PSCI code
> ARM: HYP/non-sec: add the option for a second-stage monitor
> ARM: HYP/non-sec/PSCI: emit DT nodes
>
> arch/arm/config.mk | 2 +-
> arch/arm/cpu/armv7/Makefile | 5 +
> arch/arm/cpu/armv7/nonsec_virt.S | 168
> +++++++++++++++++---------------
> arch/arm/cpu/armv7/psci.S | 102 +++++++++++++++++++
> arch/arm/cpu/armv7/virt-dt.c | 100 +++++++++++++++++++
> arch/arm/cpu/armv7/virt-v7.c | 59 ++++-------
> arch/arm/cpu/u-boot.lds | 30 ++++++
> arch/arm/include/asm/armv7.h | 11 ++-
> arch/arm/include/asm/proc-armv/ptrace.h | 2 +
> arch/arm/include/asm/psci.h | 35 +++++++
> arch/arm/include/asm/secure.h | 26 +++++
> arch/arm/lib/bootm-fdt.c | 14 ++-
> arch/arm/lib/bootm.c | 27 +++--
> arch/arm/lib/interrupts.c | 2 +-
> arch/arm/lib/sections.c | 2 +
> common/image-fdt.c | 7 +-
> include/common.h | 6 +- 17 files changed,
> 451 insertions(+), 147 deletions(-) create mode 100644
> arch/arm/cpu/armv7/psci.S create mode 100644
> arch/arm/cpu/armv7/virt-dt.c create mode 100644
> arch/arm/include/asm/psci.h create mode 100644
> arch/arm/include/asm/secure.h
>
this series fails to compile for me
CC spl/arch/arm/cpu/armv7/virt-v7.o
arch/arm/cpu/armv7/virt-v7.c: In function ‘armv7_init_nonsec’:
arch/arm/cpu/armv7/virt-v7.c:128:41: error: ‘_smp_pen’ undeclared (first use in this function)
smp_set_core_boot_addr((unsigned long)secure_ram_addr(_smp_pen), -1);
^
arch/arm/cpu/armv7/virt-v7.c:128:41: note: each undeclared identifier is reported only once for each function it appears in
arch/arm/cpu/armv7/virt-v7.c:134:3: error: ‘_nonsec_init’ undeclared (first use in this function)
secure_ram_addr(_nonsec_init)();
^
is there a series I am missing?
Dennis
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