[U-Boot] [PATCH] iomux-v3: Add support for mx6sl LVE bit

[Fabio Estevam]

On Mon, Apr 28, 2014 at 9:27 PM, Otavio Salvador
<otavio at ossystems.com.br> wrote:
> On Mon, Apr 28, 2014 at 9:14 PM, Fabio Estevam <festevam at gmail.com> wrote:
>> On Mon, Apr 28, 2014 at 8:40 PM, Otavio Salvador
>> <otavio at ossystems.com.br> wrote:
>>>>  #define PAD_CTL_HYS            (1 << 16)
>>>> +#define PAD_CTL_LVE            (1 << 17)
>>>> +#define PAD_CTL_LVE_BIT                (1 << 22)
>>>
>>> This conflicts with:
>>>
>>> #define NO_PAD_CTRL (1 << 17)
>>
>> Correct, I missed the NO_PAD_CTRL definition.
>
> So use 18?

It would also break the existing IOMUX config layout.

Bit 63 is free, so I came up with this change:

diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
index b59b802..45abee1 100644
--- a/arch/arm/imx-common/iomux-v3.c
+++ b/arch/arm/imx-common/iomux-v3.c
@@ -20,6 +20,13 @@ static void *base = (void *)IOMUXC_BASE_ADDR;
  */
 void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
 {
+#if defined CONFIG_MX6SL
+    bool lve = false;
+
+    if(pad & PAD_CTL_LVE)
+        lve = true;
+#endif
+
     u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
     u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
     u32 sel_input_ofs =
@@ -30,6 +37,12 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
         (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
     u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;

+#if defined CONFIG_MX6SL
+    /* Check whether LVE bit needs to be set */
+    if (lve)
+        pad_ctrl |= PAD_CTL_LVE_BIT;
+#endif
+
     if (mux_ctrl_ofs)
         __raw_writel(mux_mode, base + mux_ctrl_ofs);

diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h
b/arch/arm/include/asm/imx-common/iomux-v3.h
index dec11a1..5999552 100644
--- a/arch/arm/include/asm/imx-common/iomux-v3.h
+++ b/arch/arm/include/asm/imx-common/iomux-v3.h
@@ -42,7 +42,7 @@
  * MUX_MODE + SION:       36..40  (5)
  * PAD_CTRL + NO_PAD_CTRL: 41..58 (18)
  * SEL_INP:           59..62  (4)
- * reserved:             63    (1)
+ * LVE:                    63      (1)
 */

 typedef u64 iomux_v3_cfg_t;
@@ -88,6 +88,8 @@ typedef u64 iomux_v3_cfg_t;
 #ifdef CONFIG_MX6

 #define PAD_CTL_HYS        (1 << 16)
+#define PAD_CTL_LVE        0x8000000000000000
+#define PAD_CTL_LVE_BIT        (1 << 22)

 #define PAD_CTL_PUS_100K_DOWN    (0 << 14 | PAD_CTL_PUE)
 #define PAD_CTL_PUS_47K_UP    (1 << 14 | PAD_CTL_PUE)


,and in order to declare a pin as LVE we would need to do this in the
board file:

MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL) | PAD_CTL_LVE,


What do you think?