[U-Boot] [PATCH v5 01/16] arm: ls102xa: Add Freescale LS102xA SoC support

[AlisonWang]

Hi, Mark,

On Tue, Aug 19, 2014 at 03:54:50AM +0100, Alison Wang wrote:

> +int timer_init(void) 
> +{ 
> +       struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR; 
> +       unsigned long ctrl, val, freq; 
> + 
> +       /* Enable System Counter */ 
> +       writel(SYS_COUNTER_CTRL_ENABLE, &sctr->cntcr); 
> + 
> +       freq = GENERIC_TIMER_CLK; 
> +       asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));

Is CNTFRQ initialised for both CPUs? 

[Alison Wang] No, only one CPU is booted now.

If the CPUs are booted at PL1 rather than PL2, is CNTVOFF initialised to 
the same value on both CPUs? 

[Alison Wang] CNTVOFF is not initialized in the current secure mode. When
we add virtualization support and switch to non-secure mode, we will
initialize CNTVOFF to zero on both CPUs.

Thanks.
Alison



--
View this message in context: http://u-boot.10912.n7.nabble.com/PATCH-v5-0-16-arm-ls102xa-Add-Freescale-LS102xA-SoC-and-LS1021AQDS-TWR-board-support-tp186978p187075.html
Sent from the U-Boot mailing list archive at Nabble.com.