[U-Boot] [PATCH V4 08/19] arm: mx6: ddr: cleanup
Nikita Kiryanov
nikita at compulab.co.il
Wed Aug 20 14:08:55 CEST 2014
No functional changes.
Cc: Stefano Babic <sbabic at denx.de>
Cc: Tim Harvey <tharvey at gateworks.com>
Acked-by: Tim Harvey <tharvey at gateworks.com>
Signed-off-by: Nikita Kiryanov <nikita at compulab.co.il>
---
Changes in V4:
- No changes.
Changes in V3:
- No changes.
Changes in V2:
- No changes.
arch/arm/cpu/armv7/mx6/ddr.c | 272 +++++++++++++++++++++----------------------
1 file changed, 134 insertions(+), 138 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index 0434211..af91314 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -184,18 +184,18 @@ void mx6sdl_dram_iocfg(unsigned width,
*/
#define MR(val, ba, cmd, cs1) \
((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
-void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
- const struct mx6_mmdc_calibration *c,
- const struct mx6_ddr3_cfg *m)
+void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
+ const struct mx6_mmdc_calibration *calib,
+ const struct mx6_ddr3_cfg *ddr3_cfg)
{
volatile struct mmdc_p_regs *mmdc0;
volatile struct mmdc_p_regs *mmdc1;
- u32 reg;
+ u32 val;
u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */
u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
- u16 CS0_END;
+ u16 cs0_end;
u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
int clkper; /* clock period in picoseconds */
int clock; /* clock freq in mHz */
@@ -214,13 +214,12 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
clock = 400;
tcwl = 3;
}
- clkper = (1000*1000)/clock; /* ps */
+ clkper = (1000 * 1000) / clock; /* pico seconds */
todtlon = tcwl;
taxpd = tcwl;
tanpd = tcwl;
- tcwl = tcwl;
- switch (m->density) {
+ switch (ddr3_cfg->density) {
case 1: /* 1Gb per chip */
trfc = DIV_ROUND_UP(110000, clkper) - 1;
txs = DIV_ROUND_UP(120000, clkper) - 1;
@@ -239,80 +238,84 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
break;
default:
/* invalid density */
- printf("invalid chip density\n");
+ puts("invalid chip density\n");
hang();
break;
}
txpr = txs;
- switch (m->mem_speed) {
+ switch (ddr3_cfg->mem_speed) {
case 800:
- txp = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;
- tcke = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;
- if (m->pagesz == 1) {
+ txp = DIV_ROUND_UP(MAX(3 * clkper, 7500), clkper) - 1;
+ tcke = DIV_ROUND_UP(MAX(3 * clkper, 7500), clkper) - 1;
+ if (ddr3_cfg->pagesz == 1) {
tfaw = DIV_ROUND_UP(40000, clkper) - 1;
- trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1;
+ trrd = DIV_ROUND_UP(MAX(4 * clkper, 10000), clkper) - 1;
} else {
tfaw = DIV_ROUND_UP(50000, clkper) - 1;
- trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1;
+ trrd = DIV_ROUND_UP(MAX(4 * clkper, 10000), clkper) - 1;
}
break;
case 1066:
- txp = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;
- tcke = DIV_ROUND_UP(MAX(3*clkper, 5625), clkper) - 1;
- if (m->pagesz == 1) {
+ txp = DIV_ROUND_UP(MAX(3 * clkper, 7500), clkper) - 1;
+ tcke = DIV_ROUND_UP(MAX(3 * clkper, 5625), clkper) - 1;
+ if (ddr3_cfg->pagesz == 1) {
tfaw = DIV_ROUND_UP(37500, clkper) - 1;
- trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1;
+ trrd = DIV_ROUND_UP(MAX(4 * clkper, 7500), clkper) - 1;
} else {
tfaw = DIV_ROUND_UP(50000, clkper) - 1;
- trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1;
+ trrd = DIV_ROUND_UP(MAX(4 * clkper, 10000), clkper) - 1;
}
break;
case 1333:
- txp = DIV_ROUND_UP(MAX(3*clkper, 6000), clkper) - 1;
- tcke = DIV_ROUND_UP(MAX(3*clkper, 5625), clkper) - 1;
- if (m->pagesz == 1) {
+ txp = DIV_ROUND_UP(MAX(3 * clkper, 6000), clkper) - 1;
+ tcke = DIV_ROUND_UP(MAX(3 * clkper, 5625), clkper) - 1;
+ if (ddr3_cfg->pagesz == 1) {
tfaw = DIV_ROUND_UP(30000, clkper) - 1;
- trrd = DIV_ROUND_UP(MAX(4*clkper, 6000), clkper) - 1;
+ trrd = DIV_ROUND_UP(MAX(4 * clkper, 6000), clkper) - 1;
} else {
tfaw = DIV_ROUND_UP(45000, clkper) - 1;
- trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1;
+ trrd = DIV_ROUND_UP(MAX(4 * clkper, 7500), clkper) - 1;
}
break;
case 1600:
- txp = DIV_ROUND_UP(MAX(3*clkper, 6000), clkper) - 1;
- tcke = DIV_ROUND_UP(MAX(3*clkper, 5000), clkper) - 1;
- if (m->pagesz == 1) {
+ txp = DIV_ROUND_UP(MAX(3 * clkper, 6000), clkper) - 1;
+ tcke = DIV_ROUND_UP(MAX(3 * clkper, 5000), clkper) - 1;
+ if (ddr3_cfg->pagesz == 1) {
tfaw = DIV_ROUND_UP(30000, clkper) - 1;
- trrd = DIV_ROUND_UP(MAX(4*clkper, 6000), clkper) - 1;
+ trrd = DIV_ROUND_UP(MAX(4 * clkper, 6000), clkper) - 1;
} else {
tfaw = DIV_ROUND_UP(40000, clkper) - 1;
- trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1;
+ trrd = DIV_ROUND_UP(MAX(4 * clkper, 7500), clkper) - 1;
}
break;
default:
- printf("invalid memory speed\n");
+ puts("invalid memory speed\n");
hang();
break;
}
- txpdll = DIV_ROUND_UP(MAX(10*clkper, 24000), clkper) - 1;
- tcl = DIV_ROUND_UP(m->trcd, clkper/10) - 3;
- tcksre = DIV_ROUND_UP(MAX(5*clkper, 10000), clkper);
- tcksrx = tcksre;
+ txpdll = DIV_ROUND_UP(MAX(10 * clkper, 24000), clkper) - 1;
+ tcksre = DIV_ROUND_UP(MAX(5 * clkper, 10000), clkper);
taonpd = DIV_ROUND_UP(2000, clkper) - 1;
+ tcksrx = tcksre;
taofpd = taonpd;
- trp = DIV_ROUND_UP(m->trcd, clkper/10) - 1;
+ twr = DIV_ROUND_UP(15000, clkper) - 1;
+ tmrd = DIV_ROUND_UP(MAX(12 * clkper, 15000), clkper) - 1;
+ trc = DIV_ROUND_UP(ddr3_cfg->trcmin, clkper / 10) - 1;
+ tras = DIV_ROUND_UP(ddr3_cfg->trasmin, clkper / 10) - 1;
+ tcl = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 3;
+ trp = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 1;
+ twtr = ROUND(MAX(4 * clkper, 7500) / clkper, 1) - 1;
trcd = trp;
- trc = DIV_ROUND_UP(m->trcmin, clkper/10) - 1;
- tras = DIV_ROUND_UP(m->trasmin, clkper/10) - 1;
- twr = DIV_ROUND_UP(15000, clkper) - 1;
- tmrd = DIV_ROUND_UP(MAX(12*clkper, 15000), clkper) - 1;
- twtr = ROUND(MAX(4*clkper, 7500)/clkper, 1) - 1;
trtp = twtr;
- CS0_END = ((4*i->cs_density) <= 120) ? (4*i->cs_density)+7 : 127;
- debug("density:%d Gb (%d Gb per chip)\n", i->cs_density, m->density);
+ cs0_end = (4 * sysinfo->cs_density <= 120) ?
+ 4 * sysinfo->cs_density + 7 :
+ 127;
+
+ debug("density:%d Gb (%d Gb per chip)\n",
+ sysinfo->cs_density, ddr3_cfg->density);
debug("clock: %dMHz (%d ps)\n", clock, clkper);
- debug("memspd:%d\n", m->mem_speed);
+ debug("memspd:%d\n", ddr3_cfg->mem_speed);
debug("tcke=%d\n", tcke);
debug("tcksrx=%d\n", tcksrx);
debug("tcksre=%d\n", tcksre);
@@ -339,11 +342,11 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
debug("twtr=%d\n", twtr);
debug("trrd=%d\n", trrd);
debug("txpr=%d\n", txpr);
- debug("CS0_END=%d\n", CS0_END);
- debug("ncs=%d\n", i->ncs);
- debug("Rtt_wr=%d\n", i->rtt_wr);
- debug("Rtt_nom=%d\n", i->rtt_nom);
- debug("SRT=%d\n", m->SRT);
+ debug("cs0_end=%d\n", cs0_end);
+ debug("ncs=%d\n", sysinfo->ncs);
+ debug("Rtt_wr=%d\n", sysinfo->rtt_wr);
+ debug("Rtt_nom=%d\n", sysinfo->rtt_nom);
+ debug("SRT=%d\n", ddr3_cfg->SRT);
debug("tcl=%d\n", tcl);
debug("twr=%d\n", twr);
@@ -353,137 +356,130 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
* see:
* appnote, ddr3 spreadsheet
*/
- mmdc0->mpwldectrl0 = c->p0_mpwldectrl0;
- mmdc0->mpwldectrl1 = c->p0_mpwldectrl1;
- mmdc0->mpdgctrl0 = c->p0_mpdgctrl0;
- mmdc0->mpdgctrl1 = c->p0_mpdgctrl1;
- mmdc0->mprddlctl = c->p0_mprddlctl;
- mmdc0->mpwrdlctl = c->p0_mpwrdlctl;
- if (i->dsize > 1) {
- mmdc1->mpwldectrl0 = c->p1_mpwldectrl0;
- mmdc1->mpwldectrl1 = c->p1_mpwldectrl1;
- mmdc1->mpdgctrl0 = c->p1_mpdgctrl0;
- mmdc1->mpdgctrl1 = c->p1_mpdgctrl1;
- mmdc1->mprddlctl = c->p1_mprddlctl;
- mmdc1->mpwrdlctl = c->p1_mpwrdlctl;
+ mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
+ mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
+ mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
+ mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
+ mmdc0->mprddlctl = calib->p0_mprddlctl;
+ mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
+ if (sysinfo->dsize > 1) {
+ mmdc1->mpwldectrl0 = calib->p1_mpwldectrl0;
+ mmdc1->mpwldectrl1 = calib->p1_mpwldectrl1;
+ mmdc1->mpdgctrl0 = calib->p1_mpdgctrl0;
+ mmdc1->mpdgctrl1 = calib->p1_mpdgctrl1;
+ mmdc1->mprddlctl = calib->p1_mprddlctl;
+ mmdc1->mpwrdlctl = calib->p1_mpwrdlctl;
}
/* Read data DQ Byte0-3 delay */
- mmdc0->mprddqby0dl = (u32)0x33333333;
- mmdc0->mprddqby1dl = (u32)0x33333333;
- if (i->dsize > 0) {
- mmdc0->mprddqby2dl = (u32)0x33333333;
- mmdc0->mprddqby3dl = (u32)0x33333333;
+ mmdc0->mprddqby0dl = 0x33333333;
+ mmdc0->mprddqby1dl = 0x33333333;
+ if (sysinfo->dsize > 0) {
+ mmdc0->mprddqby2dl = 0x33333333;
+ mmdc0->mprddqby3dl = 0x33333333;
}
- if (i->dsize > 1) {
- mmdc1->mprddqby0dl = (u32)0x33333333;
- mmdc1->mprddqby1dl = (u32)0x33333333;
- mmdc1->mprddqby2dl = (u32)0x33333333;
- mmdc1->mprddqby3dl = (u32)0x33333333;
+
+ if (sysinfo->dsize > 1) {
+ mmdc1->mprddqby0dl = 0x33333333;
+ mmdc1->mprddqby1dl = 0x33333333;
+ mmdc1->mprddqby2dl = 0x33333333;
+ mmdc1->mprddqby3dl = 0x33333333;
}
/* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */
- reg = (i->rtt_nom == 2) ? 0x00011117 : 0x00022227;
- mmdc0->mpodtctrl = reg;
- if (i->dsize > 1)
- mmdc1->mpodtctrl = reg;
+ val = (sysinfo->rtt_nom == 2) ? 0x00011117 : 0x00022227;
+ mmdc0->mpodtctrl = val;
+ if (sysinfo->dsize > 1)
+ mmdc1->mpodtctrl = val;
/* complete calibration */
- reg = (1 << 11); /* Force measurement on delay-lines */
- mmdc0->mpmur0 = reg;
- if (i->dsize > 1)
- mmdc1->mpmur0 = reg;
+ val = (1 << 11); /* Force measurement on delay-lines */
+ mmdc0->mpmur0 = val;
+ if (sysinfo->dsize > 1)
+ mmdc1->mpmur0 = val;
/* Step 1: configuration request */
mmdc0->mdscr = (u32)(1 << 15); /* config request */
/* Step 2: Timing configuration */
- reg = (trfc << 24) | (txs << 16) | (txp << 13) | (txpdll << 9) |
- (tfaw << 4) | tcl;
- mmdc0->mdcfg0 = reg;
- reg = (trcd << 29) | (trp << 26) | (trc << 21) | (tras << 16) |
- (1 << 15) | /* trpa */
- (twr << 9) | (tmrd << 5) | tcwl;
- mmdc0->mdcfg1 = reg;
- reg = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;
- mmdc0->mdcfg2 = reg;
- reg = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) | (taxpd << 16) |
- (todtlon << 12) | (todt_idle_off << 4);
- mmdc0->mdotc = reg;
- mmdc0->mdasp = CS0_END; /* CS addressing */
+ mmdc0->mdcfg0 = (trfc << 24) | (txs << 16) | (txp << 13) |
+ (txpdll << 9) | (tfaw << 4) | tcl;
+ mmdc0->mdcfg1 = (trcd << 29) | (trp << 26) | (trc << 21) |
+ (tras << 16) | (1 << 15) /* trpa */ |
+ (twr << 9) | (tmrd << 5) | tcwl;
+ mmdc0->mdcfg2 = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;
+ mmdc0->mdotc = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) |
+ (taxpd << 16) | (todtlon << 12) | (todt_idle_off << 4);
+ mmdc0->mdasp = cs0_end; /* CS addressing */
/* Step 3: Configure DDR type */
- reg = (i->cs1_mirror << 19) | (i->walat << 16) | (i->bi_on << 12) |
- (i->mif3_mode << 9) | (i->ralat << 6);
- mmdc0->mdmisc = reg;
+ mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
+ (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
+ (sysinfo->ralat << 6);
/* Step 4: Configure delay while leaving reset */
- reg = (txpr << 16) | (i->sde_to_rst << 8) | (i->rst_to_cke << 0);
- mmdc0->mdor = reg;
+ mmdc0->mdor = (txpr << 16) | (sysinfo->sde_to_rst << 8) |
+ (sysinfo->rst_to_cke << 0);
/* Step 5: Configure DDR physical parameters (density and burst len) */
- reg = (m->rowaddr - 11) << 24 | /* ROW */
- (m->coladdr - 9) << 20 | /* COL */
- (1 << 19) | /* Burst Length = 8 for DDR3 */
- (i->dsize << 16); /* DDR data bus size */
- mmdc0->mdctl = reg;
+ mmdc0->mdctl = (ddr3_cfg->rowaddr - 11) << 24 | /* ROW */
+ (ddr3_cfg->coladdr - 9) << 20 | /* COL */
+ (1 << 19) | /* Burst Length = 8 for DDR3 */
+ (sysinfo->dsize << 16); /* DDR data bus size */
/* Step 6: Perform ZQ calibration */
- reg = (u32)0xa1390001; /* one-time HW ZQ calib */
- mmdc0->mpzqhwctrl = reg;
- if (i->dsize > 1)
- mmdc1->mpzqhwctrl = reg;
+ val = 0xa1390001; /* one-time HW ZQ calib */
+ mmdc0->mpzqhwctrl = val;
+ if (sysinfo->dsize > 1)
+ mmdc1->mpzqhwctrl = val;
/* Step 7: Enable MMDC with desired chip select */
- reg = mmdc0->mdctl |
- (1 << 31) | /* SDE_0 for CS0 */
- ((i->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
- mmdc0->mdctl = reg;
+ mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
+ ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
/* Step 8: Write Mode Registers to Init DDR3 devices */
- for (cs = 0; cs < i->ncs; cs++) {
+ for (cs = 0; cs < sysinfo->ncs; cs++) {
/* MR2 */
- reg = (i->rtt_wr & 3) << 9 | (m->SRT & 1) << 7 |
+ val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 |
((tcwl - 3) & 3) << 3;
- mmdc0->mdscr = (u32)MR(reg, 2, 3, cs);
+ mmdc0->mdscr = MR(val, 2, 3, cs);
/* MR3 */
- mmdc0->mdscr = (u32)MR(0, 3, 3, cs);
+ mmdc0->mdscr = MR(0, 3, 3, cs);
/* MR1 */
- reg = ((i->rtt_nom & 1) ? 1 : 0) << 2 |
- ((i->rtt_nom & 2) ? 1 : 0) << 6;
- mmdc0->mdscr = (u32)MR(reg, 1, 3, cs);
- reg = ((tcl - 1) << 4) | /* CAS */
+ val = ((sysinfo->rtt_nom & 1) ? 1 : 0) << 2 |
+ ((sysinfo->rtt_nom & 2) ? 1 : 0) << 6;
+ mmdc0->mdscr = MR(val, 1, 3, cs);
+ /* MR0 */
+ val = ((tcl - 1) << 4) | /* CAS */
(1 << 8) | /* DLL Reset */
((twr - 3) << 9); /* Write Recovery */
- /* MR0 */
- mmdc0->mdscr = (u32)MR(reg, 0, 3, cs);
+ mmdc0->mdscr = MR(val, 0, 3, cs);
/* ZQ calibration */
- reg = (1 << 10);
- mmdc0->mdscr = (u32)MR(reg, 0, 4, cs);
+ val = (1 << 10);
+ mmdc0->mdscr = MR(val, 0, 4, cs);
}
/* Step 10: Power down control and self-refresh */
- reg = (tcke & 0x7) << 16 |
- 5 << 12 | /* PWDT_1: 256 cycles */
- 5 << 8 | /* PWDT_0: 256 cycles */
- 1 << 6 | /* BOTH_CS_PD */
- (tcksrx & 0x7) << 3 |
- (tcksre & 0x7);
- mmdc0->mdpdc = reg;
- mmdc0->mapsr = (u32)0x00011006; /* ADOPT power down enabled */
+ mmdc0->mdpdc = (tcke & 0x7) << 16 |
+ 5 << 12 | /* PWDT_1: 256 cycles */
+ 5 << 8 | /* PWDT_0: 256 cycles */
+ 1 << 6 | /* BOTH_CS_PD */
+ (tcksrx & 0x7) << 3 |
+ (tcksre & 0x7);
+ mmdc0->mapsr = 0x00011006; /* ADOPT power down enabled */
/* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
- mmdc0->mpzqhwctrl = (u32)0xa1390003;
- if (i->dsize > 1)
- mmdc1->mpzqhwctrl = (u32)0xa1390003;
+ val = 0xa1390003;
+ mmdc0->mpzqhwctrl = val;
+ if (sysinfo->dsize > 1)
+ mmdc1->mpzqhwctrl = val;
/* Step 12: Configure and activate periodic refresh */
- reg = (1 << 14) | /* REF_SEL: Periodic refresh cycles of 32kHz */
- (7 << 11); /* REFR: Refresh Rate - 8 refreshes */
- mmdc0->mdref = reg;
+ mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */
+ (7 << 11); /* REFR: Refresh Rate - 8 refreshes */
/* Step 13: Deassert config request - init complete */
- mmdc0->mdscr = (u32)0x00000000;
+ mmdc0->mdscr = 0x00000000;
/* wait for auto-ZQ calibration to complete */
mdelay(1);
--
1.9.1
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