[U-Boot] [PATCH] mx6: Fix cacheline size

[Fabio Estevam]

mx6 is an armv7 which has 64-byte cacheline size.

Without this fix we are not able to get the FEC driver to work on mx6solox.

64-byte cacheline is also used by the kernel on ARMv7, so fix it accordingly.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/include/asm/arch-mx6/imx-regs.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 2631beb..e9e6f63 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -9,7 +9,7 @@
 
 #define ARCH_MXC
 
-#define CONFIG_SYS_CACHELINE_SIZE	32
+#define CONFIG_SYS_CACHELINE_SIZE	64
 
 #define ROMCP_ARB_BASE_ADDR             0x00000000
 #define ROMCP_ARB_END_ADDR              0x000FFFFF
-- 
1.9.1