[U-Boot] [PATCH 23/23] ARM: tegra: Enable PCIe on Jetson TK1

[Tuomas Tynkkynen]

On 18/08/14 10:16, Thierry Reding wrote:
[...]
> +static int as3722_gpio_direction_output(u8 gpio, u8 level)
> +{
> +	u8 value;
> +	int err;
> +
> +	if (gpio > 7)
> +		return -EINVAL;
> +
> +	if (level == 0)
> +		value = AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDL;
> +	else
> +		value = AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH;
> +
> +	err = as3722_write(AS3722_GPIO_CONTROL(gpio), value);
> +	if (err) {
> +		error("as3722: failed to configure GPIO#%u as output: %d\n",
> +		      gpio, err);
> +		return err;
> +	}
> +
> +	err = as3722_gpio_set(gpio, level);
> +	if (err < 0) {
> +		error("as3722: failed to set GPIO#%u high: %d\n", gpio, err);
> +		return err;
> +	}
> +
> +	return 0;
> +}

This function doesn't work correctly if the GPIO was originally configured
as inverted and low, which GPIO#2 seems to be.
(as3722_read(AS3722_GPIO_CONTROL(2), &value) returns value == 0x87)...

> +
> +int tegra_pcie_board_init(void)
> +{
[...]
> +
> +	err = as3722_gpio_direction_output(2, 1);
> +	if (err < 0) {
> +		error("as3722: failed to set GPIO#2 high: %d\n", err);
> +		return err;
> +	}
[...]

On my board, this call results in UART corruption, like this:

tegra-pcie:   non-prefetchable memory: 0x13000000-0x20000000
tegra-pcie:   prefetchable memory: 0x20000000-0x40000000
¥É½¥¹½bªÍ¥¹b2x1, 1x1 configuration
¹Í5Rþtegra-pcie: probing port 1, using 1 lanes

Likely because GPIO#2 controls the +3.3V_LP0 rail, which powers the UART
level shifters. Commenting the function call out fixes the corruption and
PCI-E still works fine.

-- 
nvpublic