[U-Boot] [PATCH 3/4] ARM: tegra: fix NV_PA_CSITE_BASE for Tegra124

[Stephen Warren]

On 02/03/2014 02:18 PM, Tom Warren wrote:
> Nice catch, fortunately I don't see this base addr used anywhere (yet) in T124.

It's used to define CSITE_CPU_DBG*_LAR, and those are used in code.

(The internal Tegra simulator I'm running complains about the incorrect
register accesses when booting U-boot)

> 
>> -----Original Message-----
>> From: Stephen Warren [mailto:swarren at wwwdotorg.org]
>> Sent: Monday, February 03, 2014 2:03 PM
>> To: u-boot at lists.denx.de; Simon Glass; Tom Warren; Stephen Warren
>> Subject: [PATCH 3/4] ARM: tegra: fix NV_PA_CSITE_BASE for Tegra124
>>
>> From: Stephen Warren <swarren at nvidia.com>
>>
>> Tegra124 moved the CSITE block's base address. Fix U-Boot to use the correct
>> address.
>>
>> Signed-off-by: Stephen Warren <swarren at nvidia.com>
>> ---
>>  arch/arm/include/asm/arch-tegra/tegra.h | 5 +++++
>>  1 file changed, 5 insertions(+)
>>
>> diff --git a/arch/arm/include/asm/arch-tegra/tegra.h
>> b/arch/arm/include/asm/arch-tegra/tegra.h
>> index 5fe19ae1ac13..d63af0e5fd9c 100644
>> --- a/arch/arm/include/asm/arch-tegra/tegra.h
>> +++ b/arch/arm/include/asm/arch-tegra/tegra.h
>> @@ -34,7 +34,12 @@
>>  #define NV_PA_PMC_BASE		(NV_PA_APB_MISC_BASE + 0xE400)
>>  #define NV_PA_EMC_BASE		(NV_PA_APB_MISC_BASE + 0xF400)
>>  #define NV_PA_FUSE_BASE		(NV_PA_APB_MISC_BASE + 0xF800)
>> +#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \
>> +	defined(CONFIG_TEGRA114)
>>  #define NV_PA_CSITE_BASE	0x70040000
>> +#else
>> +#define NV_PA_CSITE_BASE	0x70800000
>> +#endif
>>  #define TEGRA_USB_ADDR_MASK	0xFFFFC000
>>
>>  #define NV_PA_SDRC_CS0		NV_PA_SDRAM_BASE
>> --
>> 1.8.1.5
> --
> nvpublic
>