[U-Boot] [PATCH][v3] powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDS

[aneesh.bansal at freescale.com]

> -----Original Message-----
> From: Wood Scott-B07421
> Sent: Tuesday, February 04, 2014 4:32 AM
> To: Bansal Aneesh-B39320
> Cc: u-boot at lists.denx.de; Sun York-R58495; Gupta Ruchika-R66431
> Subject: Re: [PATCH][v3] powerpc/mpc85xx: SECURE BOOT- Add secure boot
> target for B4860QDS
> 
> On Mon, 2014-02-03 at 14:47 +0530, Aneesh Bansal wrote:
> > Changes:
> > 1. L2 cache is being invalidated by Boot ROM code for e6500 core.
> >    So removing the invalidation from start.S 2. Clear the LAW and
> > corresponding configuration for CPC. Boot ROM
> >    code uses it as hosekeeping area.
> > 3. For Secure boot, CPC is configured as SRAM and used as house
> >    keeping area. This configuration is to be disabled once in uboot.
> >    Earlier this disabling of CPC as SRAM was happening in cpu_init_r.
> >    As a result cache invalidation function was getting skipped in
> >    case CPC is configured as SRAM.This was causing random crashes.
> >
> > Signed-off-by: Ruchika Gupta <ruchika.gupta at freescale.com>
> > Signed-off-by: Aneesh Bansal <aneesh.bansal at freescale.com>
> > ---
> >  README                                     |  4 ++++
> >  arch/powerpc/cpu/mpc85xx/cpu_init.c        | 27
> ++++++++++++++++++++++-----
> >  arch/powerpc/cpu/mpc85xx/start.S           |  3 ++-
> >  arch/powerpc/include/asm/fsl_secure_boot.h |  6 ++++++
> >  boards.cfg                                 |  1 +
> >  5 files changed, 35 insertions(+), 6 deletions(-)
> >
> > Changes from v2:
> > Squashed with previous patch after removing the ISBC version as per
> discussion.
> > Changed the Subject Line.
> >
> > diff --git a/README b/README
> > index 176de61..3ca307f 100644
> > --- a/README
> > +++ b/README
> > @@ -428,6 +428,10 @@ The following options need to be configured:
> >  		In this mode, a single differential clock is used to supply
> >  		clocks to the sysclock, ddrclock and usbclock.
> >
> > +		CONFIG_SYS_SECURE_HKAREA_CPC
> > +		This CONFIG is defined for the SoC's in which the BootROM
> code uses
> > +		the platform cache configured as SRAM for house keeping.
> 
> What sort of house keeping?  The bootrom is finished by the time U-Boot
> starts, right?  What restrictions are there on U-Boot's use of the SRAM?
> 
> -Scott
> 
For Secure Boot, CPC is configured as SRAM by the PBI commands and BootROM uses
it for sending commands to SEC block. In U-boot CPC is to be configured as platform
cache and before doing so, the configuration of CPC as SRAM needs to be removed.