[U-Boot] [PATCH v2] Add support for B&R KWB Motherboard
Hannes Petermaier
oe5hpm at oevsv.at
Fri Feb 7 14:06:50 CET 2014
Adds support for Bernecker & Rainer Industrieelektronik GmbH KWB
Motherboard, using TI's AM3352 SoC.
Most of code is derived from TI's AM335x_EVM
Signed-off-by: Hannes Petermaier <oe5hpm at oevsv.at>
Cc: trini at ti.com
---
---
Changes for v2:
- Coding Style cleanup
- using common/shared code sections of other B&R Motherboards
- common files are also included in tsereies board
arch/arm/include/asm/arch-am33xx/cpu.h | 6 +-
board/BuR/common/bur_common.h | 22 +++
board/BuR/common/common.c | 216 ++++++++++++++++++++++++++++
board/BuR/kwb/Makefile | 12 ++
board/BuR/kwb/board.c | 240 ++++++++++++++++++++++++++++++++
board/BuR/kwb/mux.c | 195 ++++++++++++++++++++++++++
boards.cfg | 1 +
include/configs/bur_am335x_common.h | 197 ++++++++++++++++++++++++++
include/configs/kwb.h | 128 +++++++++++++++++
9 files changed, 1015 insertions(+), 2 deletions(-)
create mode 100644 board/BuR/common/bur_common.h
create mode 100644 board/BuR/common/common.c
create mode 100644 board/BuR/kwb/Makefile
create mode 100644 board/BuR/kwb/board.c
create mode 100644 board/BuR/kwb/mux.c
create mode 100644 include/configs/bur_am335x_common.h
create mode 100644 include/configs/kwb.h
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index 9febfa2..248dc4d 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -171,7 +171,8 @@ struct cm_wkuppll {
unsigned int resv11[1];
unsigned int wkup_uart0ctrl; /* offset 0xB4 */
unsigned int wkup_i2c0ctrl; /* offset 0xB8 */
- unsigned int resv12[7];
+ unsigned int wkup_adctscctrl; /* offset 0xBC */
+ unsigned int resv12[6];
unsigned int divm6dpllcore; /* offset 0xD8 */
};
@@ -221,7 +222,8 @@ struct cm_perpll {
unsigned int tpccclkctrl; /* offset 0xBC */
unsigned int dcan0clkctrl; /* offset 0xC0 */
unsigned int dcan1clkctrl; /* offset 0xC4 */
- unsigned int resv6[2];
+ unsigned int resv6;
+ unsigned int epwmss1clkctrl; /* offset 0xCC */
unsigned int emiffwclkctrl; /* offset 0xD0 */
unsigned int epwmss0clkctrl; /* offset 0xD4 */
unsigned int epwmss2clkctrl; /* offset 0xD8 */
diff --git a/board/BuR/common/bur_common.h b/board/BuR/common/bur_common.h
new file mode 100644
index 0000000..15225b0
--- /dev/null
+++ b/board/BuR/common/bur_common.h
@@ -0,0 +1,22 @@
+/*
+ * bur_comon.h
+ *
+ * common board information header for B&R boards
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm at oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BUR_COMMON_H_
+#define _BUR_COMMON_H_
+
+void blink(u32 blinks, u32 intervall, u32 pin);
+void pmicsetup(u32 mpupll);
+void enable_uart0_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_board_pin_mux(void);
+int board_eth_init(bd_t *bis);
+
+#endif
diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c
new file mode 100644
index 0000000..6d187ea
--- /dev/null
+++ b/board/BuR/common/common.c
@@ -0,0 +1,216 @@
+/*
+ * common.c
+ *
+ * common board functions for B&R boards
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm at oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <power/tps65217.h>
+#include "bur_common.h"
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+/* --------------------------------------------------------------------------*/
+void blink(u32 blinks, u32 intervall, u32 pin)
+{
+ gpio_direction_output(pin, 0);
+ int val = 0;
+
+ do {
+ val ^= 0x01;
+ gpio_set_value(pin, val);
+ mdelay(intervall);
+ } while (blinks--);
+
+ gpio_set_value(pin, 0);
+}
+#ifdef CONFIG_SPL_BUILD
+void pmicsetup(u32 mpupll)
+{
+ int mpu_vdd;
+ int usb_cur_lim;
+
+ /* setup I2C */
+ enable_i2c0_pin_mux();
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+
+ if (i2c_probe(TPS65217_CHIP_PM)) {
+ puts("PMIC (0x24) not found! skip further initalization.\n");
+ return;
+ }
+
+ /* Get the frequency which is defined by device fuses */
+ dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+ printf("detected max. frequency: %d - ", dpll_mpu_opp100.m);
+
+ if (0 != mpupll) {
+ dpll_mpu_opp100.m = MPUPLL_M_1000;
+ printf("retuning MPU-PLL to: %d MHz.\n", dpll_mpu_opp100.m);
+ } else {
+ puts("ok.\n");
+ }
+ /*
+ * Increase USB current limit to 1300mA or 1800mA and set
+ * the MPU voltage controller as needed.
+ */
+ if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
+ usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
+ mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
+ } else {
+ usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
+ mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
+ }
+
+ if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_POWER_PATH,
+ usb_cur_lim, TPS65217_USB_INPUT_CUR_LIMIT_MASK))
+ puts("tps65217_reg_write failure\n");
+
+ /* Set DCDC3 (CORE) voltage to 1.125V */
+ if (tps65217_voltage_update(TPS65217_DEFDCDC3,
+ TPS65217_DCDC_VOLT_SEL_1125MV)) {
+ puts("tps65217_voltage_update failure\n");
+ return;
+ }
+
+ /* Set CORE Frequencies to OPP100 */
+ do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+ /* Set DCDC2 (MPU) voltage */
+ if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
+ puts("tps65217_voltage_update failure\n");
+ return;
+ }
+
+ /* Set LDO3 to 1.8V */
+ if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+ TPS65217_DEFLS1,
+ TPS65217_LDO_VOLTAGE_OUT_1_8,
+ TPS65217_LDO_MASK))
+ puts("tps65217_reg_write failure\n");
+ /* Set LDO4 to 3.3V */
+ if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+ TPS65217_DEFLS2,
+ TPS65217_LDO_VOLTAGE_OUT_3_3,
+ TPS65217_LDO_MASK))
+ puts("tps65217_reg_write failure\n");
+
+ /* Set MPU Frequency to what we detected now that voltages are set */
+ do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+}
+
+void set_uart_mux_conf(void)
+{
+ enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+ enable_board_pin_mux();
+}
+
+#endif /* CONFIG_SPL_BUILD */
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static void cpsw_control(int enabled)
+{
+ /* VTP can be added here */
+ return;
+}
+
+/* describing port offsets of TI's CPSW block */
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_id = 0,
+ },
+ {
+ .slave_reg_ofs = 0x308,
+ .sliver_reg_ofs = 0xdc0,
+ .phy_id = 1,
+ },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 1,
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .bd_ram_ofs = 0x2000,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+#endif /* CONFIG_DRIVER_TI_CPSW, ... */
+
+#if defined(CONFIG_DRIVER_TI_CPSW)
+
+int board_eth_init(bd_t *bis)
+{
+ int rv = 0;
+ uint8_t mac_addr[6];
+ uint32_t mac_hi, mac_lo;
+
+ /* try reading mac address from efuse */
+ mac_lo = readl(&cdev->macid0l);
+ mac_hi = readl(&cdev->macid0h);
+ mac_addr[0] = mac_hi & 0xFF;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+ mac_addr[4] = mac_lo & 0xFF;
+ mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+ if (!getenv("ethaddr")) {
+ printf("<ethaddr> not set. Validating first E-fuse MAC ... ");
+
+ if (is_valid_ether_addr(mac_addr)) {
+ printf("using: %02X:%02X:%02X:%02X:%02X:%02X.\n",
+ mac_addr[0], mac_addr[1], mac_addr[2],
+ mac_addr[3], mac_addr[4], mac_addr[5]
+ );
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ }
+ }
+ writel(MII_MODE_ENABLE, &cdev->miisel);
+ cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII;
+ cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII;
+
+ rv = cpsw_register(&cpsw_data);
+ if (rv < 0) {
+ printf("Error %d registering CPSW switch\n", rv);
+ return 0;
+ }
+#endif /* CONFIG_DRIVER_TI_CPSW, ... */
+ return rv;
+}
+#endif /* CONFIG_DRIVER_TI_CPSW */
diff --git a/board/BuR/kwb/Makefile b/board/BuR/kwb/Makefile
new file mode 100644
index 0000000..7b04b26
--- /dev/null
+++ b/board/BuR/kwb/Makefile
@@ -0,0 +1,12 @@
+#
+# Makefile
+#
+# Copyright (C) 2014 Hannes Petermaier <oe5hpm at oevsv.at> -
+# Bernecker & Rainer Industrielektronik GmbH - http://www.br-automation.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_SPL_BUILD) += mux.o
+obj-y += ../common/common.o
+obj-y += board.o
diff --git a/board/BuR/kwb/board.c b/board/BuR/kwb/board.c
new file mode 100644
index 0000000..8aa16bc
--- /dev/null
+++ b/board/BuR/kwb/board.c
@@ -0,0 +1,240 @@
+/*
+ * board.c
+ *
+ * Board functions for B&R KWB Board
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm at oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <power/tps65217.h>
+#include "../common/bur_common.h"
+
+/* -------------------------------------------------------------------------*/
+/* -- defines for used GPIO Hardware -- */
+#define KEY (0+4)
+#define LCD_PWR (0+5)
+#define PUSH_KEY (0+31)
+#define USB2SD_NRST (32+29)
+#define USB2SD_PWR (96+13)
+/* -------------------------------------------------------------------------*/
+/* -- PSOC Resetcontroller Register defines -- */
+
+/* I2C Address of controller */
+#define RSTCTRL_ADDR 0x75
+/* Register for CTRL-word */
+#define RSTCTRL_CTRLREG 0x01
+/* Register for giving some information to VxWorks OS */
+#define RSTCTRL_SCRATCHREG 0x04
+
+/* -- defines for RSTCTRL_CTRLREG -- */
+#define RSTCTRL_FORCE_PWR_NEN 0x0404
+
+#if defined(CONFIG_SPL_BUILD)
+/* TODO: check ram-timing ! */
+static const struct ddr_data ddr3_data = {
+ .datardsratio0 = MT41K256M16HA125E_RD_DQS,
+ .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+ .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+ .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+ .cmd0csratio = MT41K256M16HA125E_RATIO,
+ .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+ .cmd1csratio = MT41K256M16HA125E_RATIO,
+ .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+ .cmd2csratio = MT41K256M16HA125E_RATIO,
+ .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+static struct emif_regs ddr3_emif_reg_data = {
+ .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+ .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+ .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+ .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+ .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+ .zq_config = MT41K256M16HA125E_ZQ_CFG,
+ .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+static const struct ctrl_ioregs ddr3_ioregs = {
+ .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+#define OSC (V_OSCK/1000000)
+const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+ unsigned int oldspeed;
+ unsigned short buf;
+
+ struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
+ struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
+ /*
+ * enable additional clocks of modules which are accessed later from
+ * VxWorks OS
+ */
+ u32 *const clk_domains[] = { 0 };
+
+ u32 *const clk_modules_kwbspecific[] = {
+ &cmwkup->wkup_adctscctrl,
+ &cmper->spi1clkctrl,
+ &cmper->dcan0clkctrl,
+ &cmper->dcan1clkctrl,
+ &cmper->epwmss0clkctrl,
+ &cmper->epwmss1clkctrl,
+ &cmper->epwmss2clkctrl,
+ 0
+ };
+ do_enable_clocks(clk_domains, clk_modules_kwbspecific, 1);
+
+ /* power-OFF LCD-Display */
+ gpio_direction_output(LCD_PWR, 0);
+
+ /* setup I2C */
+ enable_i2c0_pin_mux();
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+
+ /* power-ON 3V3 via Resetcontroller */
+ oldspeed = i2c_get_bus_speed();
+ if (0 != i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC)) {
+ buf = RSTCTRL_FORCE_PWR_NEN;
+ i2c_write(RSTCTRL_ADDR, RSTCTRL_CTRLREG, 1,
+ (uint8_t *)&buf, sizeof(buf));
+ i2c_set_bus_speed(oldspeed);
+ } else {
+ puts("ERROR: i2c_set_bus_speed failed! (turn on PWR_nEN)\n");
+ }
+
+#if defined(CONFIG_AM335X_USB0)
+ /* power on USB2SD Controller */
+ gpio_direction_output(USB2SD_PWR, 1);
+ mdelay(1);
+ /* give a reset Pulse to USB2SD Controller */
+ gpio_direction_output(USB2SD_NRST, 0);
+ mdelay(1);
+ gpio_set_value(USB2SD_NRST, 1);
+#endif
+ pmicsetup(0);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+ return &dpll_ddr3;
+}
+
+void sdram_init(void)
+{
+ config_ddr(400, &ddr3_ioregs,
+ &ddr3_data,
+ &ddr3_cmd_ctrl_data,
+ &ddr3_emif_reg_data, 0);
+}
+#endif /* CONFIG_SPL_BUILD */
+/*
+ * Basic board specific setup. Pinmux has been handled already.
+ */
+int board_init(void)
+{
+ gpmc_init();
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ const unsigned int ton = 250;
+ const unsigned int toff = 1000;
+ unsigned int cnt = 3;
+ unsigned short buf = 0xAAAA;
+ unsigned int oldspeed;
+
+ tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+ TPS65217_WLEDCTRL2, 0x32, 0xFF); /* 50% dimlevel */
+
+ if (gpio_get_value(KEY)) {
+ do {
+ /* turn on light */
+ tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+ TPS65217_WLEDCTRL1, 0x09, 0xFF);
+ mdelay(ton);
+ /* turn off light */
+ tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+ TPS65217_WLEDCTRL1, 0x01, 0xFF);
+ mdelay(toff);
+ cnt--;
+ if (!gpio_get_value(KEY) &&
+ gpio_get_value(PUSH_KEY) && 1 == cnt) {
+ puts("updating from USB ...\n");
+ setenv("bootcmd", "run usbupdate");
+ break;
+ } else if (!gpio_get_value(KEY)) {
+ break;
+ }
+ } while (cnt);
+ }
+
+ switch (cnt) {
+ case 0:
+ puts("3 blinks ... entering BOOT mode.\n");
+ buf = 0x0000;
+ break;
+ case 1:
+ puts("2 blinks ... entering DIAGNOSE mode.\n");
+ buf = 0x0F0F;
+ break;
+ case 2:
+ puts("1 blinks ... entering SERVICE mode.\n");
+ buf = 0xB4B4;
+ break;
+ case 3:
+ puts("0 blinks ... entering RUN mode.\n");
+ buf = 0x0404;
+ break;
+ }
+ mdelay(ton);
+ /* turn on light */
+ tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+ TPS65217_WLEDCTRL1, 0x09, 0xFF);
+ /* write bootinfo into scratchregister of resetcontroller */
+ oldspeed = i2c_get_bus_speed();
+ if (0 != i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC)) {
+ i2c_write(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1,
+ (uint8_t *)&buf, sizeof(buf));
+ i2c_set_bus_speed(oldspeed);
+ } else {
+ puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n");
+ }
+ /*
+ * reset VBAR registers to its reset location, VxWorks 6.9.3.2 does
+ * expect that vectors are there, original u-boot moves them to _start
+ */
+ __asm__("ldr r0,=0x20000");
+ __asm__("mcr p15, 0, r0, c12, c0, 0"); /* Set VBAR */
+
+ return 0;
+}
+#endif /* CONFIG_BOARD_LATE_INIT */
diff --git a/board/BuR/kwb/mux.c b/board/BuR/kwb/mux.c
new file mode 100644
index 0000000..1a5ffd5
--- /dev/null
+++ b/board/BuR/kwb/mux.c
@@ -0,0 +1,195 @@
+/*
+ * mux.c
+ *
+ * Pinmux Setting for B&R LEIT Board(s)
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm at oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+
+static struct module_pin_mux usb0_pin_mux[] = {
+ {OFFSET(usb0_id), (MODE(0) | RXACTIVE)},
+ /* USB0 DrvBus Receiver disable (from romcode 0x20) */
+ {OFFSET(usb0_drvvbus), (MODE(0))},
+ /* USB1 DrvBus as GPIO due to HW-Workaround */
+ {OFFSET(usb1_drvvbus), (MODE(7))},
+ {-1},
+};
+static struct module_pin_mux spi1_pin_mux[] = {
+ /* SPI1_SCLK */
+ {OFFSET(mcasp0_aclkx), MODE(3) | PULLUDEN | RXACTIVE},
+ /* SPI1_D0 */
+ {OFFSET(mcasp0_fsx), MODE(3) | PULLUDEN | RXACTIVE},
+ /* SPI1_D1 */
+ {OFFSET(mcasp0_axr0), MODE(3) | PULLUDEN | RXACTIVE},
+ /* SPI1_CS0 */
+ {OFFSET(mcasp0_ahclkr), MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE},
+ {-1},
+};
+
+static struct module_pin_mux dcan0_pin_mux[] = {
+ /* DCAN0 TX */
+ {OFFSET(uart1_ctsn), MODE(2) | PULLUDEN | PULLUP_EN},
+ /* DCAN0 RX */
+ {OFFSET(uart1_rtsn), MODE(2) | RXACTIVE},
+ {-1},
+};
+
+static struct module_pin_mux dcan1_pin_mux[] = {
+ /* DCAN1 TX */
+ {OFFSET(uart1_rxd), MODE(2) | PULLUDEN | PULLUP_EN},
+ /* DCAN1 RX */
+ {OFFSET(uart1_txd), MODE(2) | RXACTIVE},
+ {-1},
+};
+
+static struct module_pin_mux gpios[] = {
+ /* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
+ {OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS)},
+ /* GPIO0_4 (SPI D1) - TA602 */
+ {OFFSET(spi0_d1), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO0_5 (SPI CS0) - DISPLAY_ON_OFF */
+ {OFFSET(spi0_cs0), (MODE(7) | PULLUDDIS)},
+ /* GPIO0_7 (PWW0 OUT) - CAN TERM */
+ {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO0_19 (DMA_INTR0) - CLKOUT SYS */
+ {OFFSET(xdma_event_intr0), (MODE(7) | RXACTIVE)},
+ /* GPIO0_20 (DMA_INTR1) - SPI1 nCS1 */
+ {OFFSET(xdma_event_intr1), (MODE(7) | PULLUDEN | PULLUP_EN)},
+ /* GPIO0_30 (GPMC_WAIT0) - TA601 */
+ {OFFSET(gpmc_wait0), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO0_31 (GPMC_nWP) - SW601 PushButton */
+ {OFFSET(gpmc_wpn), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO1_28 (GPMC_nWE) - FRAM_nWP */
+ {OFFSET(gpmc_be1n), (MODE(7) | PULLUDDIS)},
+ /* GPIO2_0 (GPMC_nCS3) - VBAT_OK */
+ {OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) },
+ /* GPIO2_2 (GPMC_nADV_ALE) - DCOK */
+ {OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO2_4 (GPMC_nWE) - TST_BAST */
+ {OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS)},
+ /* GPIO3_18 (MCASP0_ACLKR) - SW601 CNTup, mapped to Counter eQEB0A_in */
+ {OFFSET(mcasp0_aclkr), (MODE(1) | PULLUDDIS | RXACTIVE)},
+ /* GPIO3_19 (MCASP0_FSR) - SW601 CNTdown, mapped to Counter eQEB0B_in */
+ {OFFSET(mcasp0_fsr), (MODE(1) | PULLUDDIS | RXACTIVE)},
+ /* GPIO3_20 (MCASP0_AXR1) - SW601 CNTdown, map to Counter eQEB0_index */
+ {OFFSET(mcasp0_axr1), (MODE(1) | PULLUDDIS | RXACTIVE)},
+ {-1},
+};
+
+static struct module_pin_mux uart0_pin_mux[] = {
+ /* UART0_CTS */
+ {OFFSET(uart0_ctsn), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+ /* UART0_RXD */
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+ /* UART0_TXD */
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
+ {-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+ /* I2C_DATA */
+ {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+ /* I2C_SCLK */
+ {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+ {-1},
+};
+
+static struct module_pin_mux mii1_pin_mux[] = {
+ {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
+ {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
+ {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
+ {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
+ {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
+ {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
+ {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
+ {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
+ {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
+ {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
+ {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
+ {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
+ {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {-1},
+};
+
+static struct module_pin_mux mmc1_pin_mux[] = {
+ {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
+ {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
+ {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
+ {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
+ {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
+ {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
+ {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
+ {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
+
+ {-1},
+};
+
+static struct module_pin_mux lcd_pin_mux[] = {
+ {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */
+ {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */
+ {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */
+ {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */
+ {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */
+ {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */
+ {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */
+ {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */
+ {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */
+ {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */
+ {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */
+ {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */
+ {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */
+ {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */
+ {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */
+ {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */
+
+ {OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */
+ {OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */
+ {OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */
+ {OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */
+ {OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */
+ {OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */
+ {OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */
+ {OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */
+
+ {OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */
+ {OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */
+ {OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
+ {OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */
+
+ {-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+ configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+ configure_module_pin_mux(i2c0_pin_mux);
+ configure_module_pin_mux(mii1_pin_mux);
+ configure_module_pin_mux(usb0_pin_mux);
+ configure_module_pin_mux(spi1_pin_mux);
+ configure_module_pin_mux(dcan0_pin_mux);
+ configure_module_pin_mux(dcan1_pin_mux);
+ configure_module_pin_mux(mmc1_pin_mux);
+ configure_module_pin_mux(lcd_pin_mux);
+ configure_module_pin_mux(gpios);
+}
diff --git a/boards.cfg b/boards.cfg
index 706ec96..016a94e 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -255,6 +255,7 @@ Active arm armv7 am33xx phytec pcm051
Active arm armv7 am33xx siemens dxr2 dxr2 - Roger Meier <r.meier at siemens.com>
Active arm armv7 am33xx siemens pxm2 pxm2 - Roger Meier <r.meier at siemens.com>
Active arm armv7 am33xx siemens rut rut - Roger Meier <r.meier at siemens.com>
+Active arm armv7 am33xx BuR kwb kwb kwb:SERIAL1,CONS_INDEX=1 Hannes Petermaier <hannes.petermaier at br-automation.com>
Active arm armv7 am33xx ti am335x am335x_boneblack am335x_evm:SERIAL1,CONS_INDEX=1,EMMC_BOOT Tom Rini <trini at ti.com>
Active arm armv7 am33xx ti am335x am335x_evm am335x_evm:SERIAL1,CONS_INDEX=1,NAND Tom Rini <trini at ti.com>
Active arm armv7 am33xx ti am335x am335x_evm_nor am335x_evm:SERIAL1,CONS_INDEX=1,NAND,NOR Tom Rini <trini at ti.com>
diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h
new file mode 100644
index 0000000..1f57bd2
--- /dev/null
+++ b/include/configs/bur_am335x_common.h
@@ -0,0 +1,197 @@
+/*
+ * bur_am335x_common.h
+ *
+ * common parts used by B&R AM335x based boards
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm at oevsv.at> -
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __BUR_AM335X_COMMON_H__
+#define __BUR_AM335X_COMMON_H__
+/* ------------------------------------------------------------------------- */
+#define CONFIG_AM33XX
+#define CONFIG_OMAP
+#define CONFIG_OMAP_COMMON
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
+
+/* Timer information */
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
+
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_POWER_TPS65217
+
+#define CONFIG_SYS_NO_FLASH /* have no NOR-flash */
+
+#include <asm/arch/omap.h>
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK 48000000
+#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
+#define CONFIG_BAUDRATE 115200
+
+/* Network defines */
+#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_NET_RETRY_COUNT 4
+#define CONFIG_CMD_PING
+#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */
+#define CONFIG_MII /* Required in net/eth.c */
+#define CONFIG_SPL_ETH_SUPPORT
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ADDR 1
+#define CONFIG_PHY_NATSEMI
+#define CONFIG_SPL_NET_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT /* used for a fetching MAC-Address */
+#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"
+
+/*
+ * SPL related defines. The Public RAM memory map the ROM defines the
+ * area between 0x402F0400 and 0x4030B800 as a download area and
+ * 0x4030B800 to 0x4030CE00 as a public stack area. The ROM also
+ * supports X-MODEM loading via UART, and we leverage this and then use
+ * Y-MODEM to load u-boot.img, when booted over UART.
+ */
+#define CONFIG_SPL_TEXT_BASE 0x402F0400
+#define CONFIG_SPL_MAX_SIZE (0x4030B800 - CONFIG_SPL_TEXT_BASE)
+
+/*
+ * Since SPL did pll and ddr initialization for us,
+ * we don't need to do it twice.
+ */
+#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif /* !CONFIG_SPL_BUILD, ... */
+/*
+ * Our DDR memory always starts at 0x80000000 and U-Boot shall have
+ * relocated itself to higher in memory by the time this value is used.
+ */
+#define CONFIG_SYS_LOAD_ADDR 0x80000000
+/*
+ * ----------------------------------------------------------------------------
+ * DDR information. We say (for simplicity) that we have 1 bank,
+ * always, even when we have more. We always start at 0x80000000,
+ * and we place the initial stack pointer in our SRAM.
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
+ GENERATED_GBL_DATA_SIZE)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_OMAP24XX
+
+/* GPIO */
+#define CONFIG_OMAP_GPIO
+#define CONFIG_CMD_GPIO
+/*
+ * ----------------------------------------------------------------------------
+ * The following are general good-enough settings for U-Boot. We set a
+ * large malloc pool as we generally have a lot of DDR, and we opt for
+ * function over binary size in the main portion of U-Boot as this is
+ * generally easily constrained later if needed. We enable the config
+ * options that give us information in the environment about what board
+ * we are on so we do not need to rely on the command prompt. We set a
+ * console baudrate of 115200 and use the default baud rate table.
+ */
+#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT "U-Boot (BuR V2.0)# "
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_ENV_OVERWRITE /* Overwrite ethaddr / serial# */
+
+/* As stated above, the following choices are optional. */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_VERSION_VARIABLE
+
+/* We set the max number of command args high to avoid HUSH bugs. */
+#define CONFIG_SYS_MAXARGS 64
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 512
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE +\
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+/*
+ * For commands to use, we take the default list and add a few other
+ * useful commands. Note that we must have set CONFIG_SYS_NO_FLASH
+ * prior to this include, in order to skip a few commands. When we do
+ * have flash, if we expect these commands they must be enabled in that
+ * config. If desired, a specific list of desired commands can be used
+ * instead.
+ */
+#include <config_cmd_default.h>
+/* undefine commands, which we do not need */
+#undef CONFIG_CMD_EDITENV
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_ITEST
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+#undef CONFIG_CMD_CRC32
+/* define command we need always */
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_SOURCE
+
+/*
+ * Our platforms make use of SPL to initalize the hardware (primarily
+ * memory) enough for full U-Boot to be loaded. We also support Falcon
+ * Mode so that the Linux kernel can be booted directly from SPL
+ * instead, if desired. We make use of the general SPL framework found
+ * under common/spl/. Given our generally common memory map, we set a
+ * number of related defaults and sizes here.
+ */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+/*
+ * Place the image at the start of the ROM defined image space.
+ * We limit our size to the ROM-defined downloaded image area, and use the
+ * rest of the space for stack. We load U-Boot itself into memory at
+ * 0x80800000 for legacy reasons (to not conflict with older SPLs). We
+ * have our BSS be placed 1MiB after this, to allow for the default
+ * Linux kernel address of 0x80008000 to work, in the Falcon Mode case.
+ * We have the SPL malloc pool at the end of the BSS area.
+ *
+ * ----------------------------------------------------------------------------
+ */
+#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
+#undef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0x80800000
+#define CONFIG_SPL_BSS_START_ADDR 0x80A00000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
+#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
+ CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
+
+/* General parts of the framework, required. */
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_YMODEM_SUPPORT
+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
+
+#endif /* ! __BUR_AM335X_COMMON_H__ */
diff --git a/include/configs/kwb.h b/include/configs/kwb.h
new file mode 100644
index 0000000..0f631c0
--- /dev/null
+++ b/include/configs/kwb.h
@@ -0,0 +1,128 @@
+/*
+ * kwb.h
+ *
+ * specific parts for B&R KWB Motherboard
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm at oevsv.at> -
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_KWB_H__
+#define __CONFIG_KWB_H__
+
+#include <configs/bur_am335x_common.h>
+/* ------------------------------------------------------------------------- */
+/* Clock Defines */
+#define V_OSCK 26000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK)
+
+#define CONFIG_POWER_TPS65217
+
+#define CONFIG_MACH_TYPE 3589
+/* I2C IP block */
+#define CONFIG_SYS_OMAP24_I2C_SPEED_PSOC 20000
+
+/* GPIO */
+#define CONFIG_SPL_GPIO_SUPPORT
+
+/* MMC/SD IP block */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_CMD_MMC
+#define CONFIG_SUPPORT_EMMC_BOOT
+/* RAW SD card / eMMC locations. */
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /*addr. 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
+#define CONFIG_SPL_MMC_SUPPORT
+
+#undef CONFIG_SPL_OS_BOOT
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_SYS_SPL_ARGS_ADDR 0x80F80000
+
+/* RAW SD card / eMMC */
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */
+
+#endif /* CONFIG_SPL_OS_BOOT */
+
+/* Always 128 KiB env size */
+#define CONFIG_ENV_SIZE (128 << 10)
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "autoload=0\0" \
+ "loadaddr=0x80100000\0" \
+ "bootfile=arimg\0" \
+ "usbboot=echo Booting from USB-Stick ...; " \
+ "usb start; " \
+ "fatload usb 0 ${loadaddr} ${bootfile}; " \
+ "usb stop; " \
+ "go ${loadaddr};\0" \
+ "netboot=echo Booting from network ...; " \
+ "setenv autoload 0; " \
+ "dhcp; " \
+ "tftp ${loadaddr} arimg; " \
+ "go ${loadaddr}\0" \
+ "usbupdate=echo Updating UBOOT from USB-Stick ...; " \
+ "usb start; " \
+ "fatload usb 0 0x80000000 updateubootusb.img; " \
+ "source;\0" \
+ "netupdate=echo Updating UBOOT from Network (TFTP) ...; " \
+ "setenv autoload 0; " \
+ "dhcp;" \
+ "tftp 0x80000000 updateUBOOT.img;" \
+ "source;\0"
+#endif /* !CONFIG_SPL_BUILD*/
+
+#define CONFIG_BOOTCOMMAND \
+ "run usbupdate;"
+#define CONFIG_BOOTDELAY 1 /* TODO: für release auf 0 setzen */
+
+/* undefine command which we not need here */
+#undef CONFIG_BOOTM_LINUX
+#undef CONFIG_BOOTM_NETBSD
+#undef CONFIG_BOOTM_PLAN9
+#undef CONFIG_BOOTM_RTEMS
+#undef CONFIG_GZIP
+#undef CONFIG_ZLIB
+#undef CONFIG_CMD_CRC32
+
+/* USB configuration */
+#define CONFIG_USB_MUSB_DSPS
+#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_MUSB_PIO_ONLY
+#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT
+/* attention! not only for gadget, enables also highspeed in hostmode */
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_MUSB_HOST
+#define CONFIG_AM335X_USB0
+#define CONFIG_AM335X_USB0_MODE MUSB_HOST
+
+#ifdef CONFIG_MUSB_HOST
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#endif /* CONFIG_MUSB_HOST */
+
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 1
+#define CONFIG_SYS_MMC_ENV_PART 2
+#define CONFIG_ENV_OFFSET 0x40000 /* TODO: Adresse definieren */
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+/*
+ * Common filesystems support. When we have removable storage we
+ * enabled a number of useful commands and support.
+ */
+#if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE)
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+#define CONFIG_FAT_WRITE
+#define CONFIG_CMD_FS_GENERIC
+#endif /* CONFIG_MMC, ... */
+
+#endif /* ! __CONFIG_TSERIES_H__ */
--
1.7.9.5
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