[U-Boot] [PATCH 1/3] armv8/cache: Consolidate setting for MAIR and TCR

[FengHua]

hi York,

> -----Original Messages-----
> From: "York Sun" <yorksun at freescale.com>
> Sent Time: 2014-02-11 05:55:52 (Tuesday)
> To: albert.u.boot at aribaud.net
> Cc: scottwood at freescale.com, "York Sun" <yorksun at freescale.com>, "David Feng" <fenghua at phytium.com.cn>
> Subject: [PATCH 1/3] armv8/cache: Consolidate setting for MAIR and TCR
> 
> Move setting for MAIR and TCR to cache_v8.c, to avoid conflict with
> sub-architecture.
> 
> Signed-off-by: York Sun <yorksun at freescale.com>
> CC: David Feng <fenghua at phytium.com.cn>
> ---
>  arch/arm/cpu/armv8/cache_v8.c |   22 +++++++++++++++++++---
>  arch/arm/cpu/armv8/start.S    |   22 ----------------------
>  2 files changed, 19 insertions(+), 25 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
> index 131fdab..7acae1b 100644
> --- a/arch/arm/cpu/armv8/cache_v8.c
> +++ b/arch/arm/cpu/armv8/cache_v8.c
> @@ -45,15 +45,31 @@ static void mmu_setup(void)
>  
>  	/* load TTBR0 */
>  	el = current_el();
> -	if (el == 1)
> +	if (el == 1) {
>  		asm volatile("msr ttbr0_el1, %0"
>  			     : : "r" (gd->arch.tlb_addr) : "memory");
> -	else if (el == 2)
> +		asm volatile("msr tcr_el1, %0"
> +			     : : "r" (TCR_FLAGS | TCR_EL1_IPS_BITS)
> +			     : "memory");
> +		asm volatile("msr mair_el1, %0"
> +			     : : "r" (MEMORY_ATTRIBUTES) : "memory");
> +	} else if (el == 2) {
>  		asm volatile("msr ttbr0_el2, %0"
>  			     : : "r" (gd->arch.tlb_addr) : "memory");
> -	else
> +		asm volatile("msr tcr_el2, %0"
> +			     : : "r" (TCR_FLAGS | TCR_EL2_IPS_BITS)
> +			     : "memory");
> +		asm volatile("msr mair_el2, %0"
> +			     : : "r" (MEMORY_ATTRIBUTES) : "memory");
> +	} else {
>  		asm volatile("msr ttbr0_el3, %0"
>  			     : : "r" (gd->arch.tlb_addr) : "memory");
> +		asm volatile("msr tcr_el3, %0"
> +			     : : "r" (TCR_FLAGS | TCR_EL2_IPS_BITS)
> +			     : "memory");
> +		asm volatile("msr mair_el3, %0"
> +			     : : "r" (MEMORY_ATTRIBUTES) : "memory");
> +	}
>  
>  	/* enable the mmu */
>  	set_sctlr(get_sctlr() | CR_M);
> diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
> index bcc2603..90daa4d 100644
> --- a/arch/arm/cpu/armv8/start.S
> +++ b/arch/arm/cpu/armv8/start.S
> @@ -128,28 +128,6 @@ ENTRY(c_runtime_cpu_setup)
>  	isb	sy
>  #endif
>  
> -#ifndef CONFIG_SYS_DCACHE_OFF
> -	/*
> -	 * Setup MAIR and TCR.
> -	 */
> -	ldr	x0, =MEMORY_ATTRIBUTES
> -	ldr	x1, =TCR_FLAGS
> -
> -	switch_el x2, 3f, 2f, 1f
> -3:	orr	x1, x1, TCR_EL3_IPS_BITS
> -	msr	mair_el3, x0
> -	msr	tcr_el3, x1
> -	b	0f
> -2:	orr	x1, x1, TCR_EL2_IPS_BITS
> -	msr	mair_el2, x0
> -	msr	tcr_el2, x1
> -	b	0f
> -1:	orr	x1, x1, TCR_EL1_IPS_BITS
> -	msr	mair_el1, x0
> -	msr	tcr_el1, x1
> -0:
> -#endif
> -
>  	/* Relocate vBAR */
>  	adr	x0, vectors
>  	switch_el x1, 3f, 2f, 1f
> -- 
> 1.7.9.5
> 
This will be better.  Acked.