[U-Boot] [PATCH v3] powerpc/t2081qds: Add T2081 QDS board support

Shengzhou Liu Shengzhou.Liu at freescale.com
Fri Feb 21 06:16:19 CET 2014


T2081 QDS is a high-performance computing evaluation, development and
test platform supporting the T2081 QorIQ Power Architecture processor.

T2081QDS board Overview
-----------------------
- T2081 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
- 2MB shared L2 and 512KB L3 CoreNet platform cache (CPC)
- CoreNet fabric supporting coherent and noncoherent transactions with
  prioritization and bandwidth allocation
- 32-/64-bit DDR3/DDR3LP SDRAM memory controller with ECC and interleaving
- Ethernet interfaces:
  - Two on-board 10M/100M/1G bps RGMII ports
  - Two 10Gbps XFI with on-board SFP+ cage
  - 1Gbps/2.5Gbps SGMII Riser card
  - 10Gbps XAUI Riser card
- Accelerator:
  - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
- SerDes:
  - 8 lanes up to 10.3125GHz
  - Supports SGMII, HiGig, XFI, XAUI and Aurora debug,
- IFC:
  - 512MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA
- eSPI:
  - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
- USB:
  - Two USB2.0 ports with internal PHY (one Type-A + one micro Type mini-AB)
- PCIe:
  - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
- eSDHC:
  - Supports various SD/SDHC/SDXC/eMMC devices with adapter cards and
    voltage translators
- I2C:
  - Four I2C controllers.
- UART:
  - Dual 4-pins UART serial ports

Signed-off-by: Shengzhou Liu <Shengzhou.Liu at freescale.com>
---
v3: add fixup devicetree for t2081qds.
v2: some update for serdes and network configuration.

 board/freescale/t2080qds/Makefile         |  12 -
 board/freescale/t2080qds/ddr.c            | 119 -----
 board/freescale/t2080qds/ddr.h            |  72 ---
 board/freescale/t2080qds/eth_t2080qds.c   | 517 -------------------
 board/freescale/t2080qds/law.c            |  34 --
 board/freescale/t2080qds/pci.c            |  23 -
 board/freescale/t2080qds/t2080_pbi.cfg    |  41 --
 board/freescale/t2080qds/t2080_rcw.cfg    |   8 -
 board/freescale/t2080qds/t2080qds.c       | 378 --------------
 board/freescale/t2080qds/t2080qds.h       |  13 -
 board/freescale/t2080qds/t2080qds_qixis.h |  47 --
 board/freescale/t2080qds/tlb.c            | 146 ------
 board/freescale/t208xqds/Makefile         |  14 +
 board/freescale/t208xqds/ddr.c            | 119 +++++
 board/freescale/t208xqds/ddr.h            |  72 +++
 board/freescale/t208xqds/eth_t208xqds.c   | 648 ++++++++++++++++++++++++
 board/freescale/t208xqds/law.c            |  34 ++
 board/freescale/t208xqds/pci.c            |  23 +
 board/freescale/t208xqds/t2080_rcw.cfg    |   8 +
 board/freescale/t208xqds/t2081_rcw.cfg    |   8 +
 board/freescale/t208xqds/t208x_pbi.cfg    |  41 ++
 board/freescale/t208xqds/t208xqds.c       | 459 +++++++++++++++++
 board/freescale/t208xqds/t208xqds.h       |  13 +
 board/freescale/t208xqds/t208xqds_qixis.h |  49 ++
 board/freescale/t208xqds/tlb.c            | 146 ++++++
 boards.cfg                                |  15 +-
 include/configs/T2080QDS.h                | 804 -----------------------------
 include/configs/T208xQDS.h                | 817 ++++++++++++++++++++++++++++++
 28 files changed, 2461 insertions(+), 2219 deletions(-)
 delete mode 100644 board/freescale/t2080qds/Makefile
 delete mode 100644 board/freescale/t2080qds/ddr.c
 delete mode 100644 board/freescale/t2080qds/ddr.h
 delete mode 100644 board/freescale/t2080qds/eth_t2080qds.c
 delete mode 100644 board/freescale/t2080qds/law.c
 delete mode 100644 board/freescale/t2080qds/pci.c
 delete mode 100644 board/freescale/t2080qds/t2080_pbi.cfg
 delete mode 100644 board/freescale/t2080qds/t2080_rcw.cfg
 delete mode 100644 board/freescale/t2080qds/t2080qds.c
 delete mode 100644 board/freescale/t2080qds/t2080qds.h
 delete mode 100644 board/freescale/t2080qds/t2080qds_qixis.h
 delete mode 100644 board/freescale/t2080qds/tlb.c
 create mode 100644 board/freescale/t208xqds/Makefile
 create mode 100644 board/freescale/t208xqds/ddr.c
 create mode 100644 board/freescale/t208xqds/ddr.h
 create mode 100644 board/freescale/t208xqds/eth_t208xqds.c
 create mode 100644 board/freescale/t208xqds/law.c
 create mode 100644 board/freescale/t208xqds/pci.c
 create mode 100644 board/freescale/t208xqds/t2080_rcw.cfg
 create mode 100644 board/freescale/t208xqds/t2081_rcw.cfg
 create mode 100644 board/freescale/t208xqds/t208x_pbi.cfg
 create mode 100644 board/freescale/t208xqds/t208xqds.c
 create mode 100644 board/freescale/t208xqds/t208xqds.h
 create mode 100644 board/freescale/t208xqds/t208xqds_qixis.h
 create mode 100644 board/freescale/t208xqds/tlb.c
 delete mode 100644 include/configs/T2080QDS.h
 create mode 100644 include/configs/T208xQDS.h

diff --git a/board/freescale/t2080qds/Makefile b/board/freescale/t2080qds/Makefile
deleted file mode 100644
index 0b8747b..0000000
--- a/board/freescale/t2080qds/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Copyright 2013 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier:      GPL-2.0+
-#
-
-obj-$(CONFIG_T2080QDS) += t2080qds.o
-obj-$(CONFIG_T2080QDS) += eth_t2080qds.o
-obj-$(CONFIG_PCI)      += pci.o
-obj-y   += ddr.o
-obj-y   += law.o
-obj-y   += tlb.o
diff --git a/board/freescale/t2080qds/ddr.c b/board/freescale/t2080qds/ddr.c
deleted file mode 100644
index ed1334d..0000000
--- a/board/freescale/t2080qds/ddr.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 or later as published by the Free Software Foundation.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <hwconfig.h>
-#include <asm/mmu.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/fsl_law.h>
-#include "ddr.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
-	ulong ddr_freq;
-
-	if (ctrl_num > 1) {
-		printf("Not supported controller number %d\n", ctrl_num);
-		return;
-	}
-	if (!pdimm->n_ranks)
-		return;
-
-	/*
-	 * we use identical timing for all slots. If needed, change the code
-	 * to  pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
-	 */
-	if (popts->registered_dimm_en)
-		pbsp = rdimms[0];
-	else
-		pbsp = udimms[0];
-
-	/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
-	 * freqency and n_banks specified in board_specific_parameters table.
-	 */
-	ddr_freq = get_ddr_freq(0) / 1000000;
-	while (pbsp->datarate_mhz_high) {
-		if (pbsp->n_ranks == pdimm->n_ranks &&
-		    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
-			if (ddr_freq <= pbsp->datarate_mhz_high) {
-				popts->clk_adjust = pbsp->clk_adjust;
-				popts->wrlvl_start = pbsp->wrlvl_start;
-				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
-				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
-				goto found;
-			}
-			pbsp_highest = pbsp;
-		}
-		pbsp++;
-	}
-
-	if (pbsp_highest) {
-		printf("Error: board specific timing not found");
-		printf("for data rate %lu MT/s\n", ddr_freq);
-		printf("Trying to use the highest speed (%u) parameters\n",
-		       pbsp_highest->datarate_mhz_high);
-		popts->clk_adjust = pbsp_highest->clk_adjust;
-		popts->wrlvl_start = pbsp_highest->wrlvl_start;
-		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
-		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
-	} else {
-		panic("DIMM is not supported by this board");
-	}
-found:
-	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
-		"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
-		"wrlvl_ctrl_3 0x%x\n",
-		pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
-		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
-		pbsp->wrlvl_ctl_3);
-
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 0;
-	/*
-	 * Write leveling override
-	 */
-	popts->wrlvl_override = 1;
-	popts->wrlvl_sample = 0xf;
-
-	/*
-	 * Rtt and Rtt_WR override
-	 */
-	popts->rtt_override = 0;
-
-	/* Enable ZQ calibration */
-	popts->zq_en = 1;
-
-	/* DHC_EN =1, ODT = 75 Ohm */
-	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
-	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
-}
-
-phys_size_t initdram(int board_type)
-{
-	phys_size_t dram_size;
-
-	puts("Initializing....using SPD\n");
-
-	dram_size = fsl_ddr_sdram();
-
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-	dram_size *= 0x100000;
-
-	puts("    DDR: ");
-	return dram_size;
-}
diff --git a/board/freescale/t2080qds/ddr.h b/board/freescale/t2080qds/ddr.h
deleted file mode 100644
index 9fc879a..0000000
--- a/board/freescale/t2080qds/ddr.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#ifndef __DDR_H__
-#define __DDR_H__
-struct board_specific_parameters {
-	u32 n_ranks;
-	u32 datarate_mhz_high;
-	u32 rank_gb;
-	u32 clk_adjust;
-	u32 wrlvl_start;
-	u32 wrlvl_ctl_2;
-	u32 wrlvl_ctl_3;
-};
-
-/*
- * These tables contain all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-
-static const struct board_specific_parameters udimm0[] = {
-	/*
-	 * memory controller 0
-	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl |
-	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
-	 */
-	{2,  1200, 2, 5,     7, 0x0808090a, 0x0b0c0c0a},
-	{2,  1500, 2, 5,     6, 0x07070809, 0x0a0b0b09},
-	{2,  1600, 2, 5,     8, 0x090b0b0d, 0x0d0e0f0b},
-	{2,  1700, 2, 4,     7, 0x080a0a0c, 0x0c0d0e0a},
-	{2,  1900, 2, 5,     9, 0x0a0b0c0e, 0x0f10120c},
-	{2,  2140, 2, 4,     8, 0x090a0b0d, 0x0e0f110b},
-	{1,  1200, 2, 5,     7, 0x0808090a, 0x0b0c0c0a},
-	{1,  1500, 2, 5,     6, 0x07070809, 0x0a0b0b09},
-	{1,  1600, 2, 5,     8, 0x090b0b0d, 0x0d0e0f0b},
-	{1,  1700, 2, 4,     7, 0x080a0a0c, 0x0c0d0e0a},
-	{1,  1900, 2, 5,     9, 0x0a0b0c0e, 0x0f10120c},
-	{1,  2140, 2, 4,     8, 0x090a0b0d, 0x0e0f110b},
-	{}
-};
-
-static const struct board_specific_parameters rdimm0[] = {
-	/*
-	 * memory controller 0
-	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl |
-	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
-	 */
-	/* TODO: need tuning these parameters if RDIMM is used */
-	{4,  1350, 0, 5,     9, 0x08070605, 0x06070806},
-	{4,  1666, 0, 5,    11, 0x0a080706, 0x07090906},
-	{4,  2140, 0, 5,    12, 0x0b090807, 0x080a0b07},
-	{2,  1350, 0, 5,     9, 0x08070605, 0x06070806},
-	{2,  1666, 0, 5,    11, 0x0a090806, 0x08090a06},
-	{2,  2140, 0, 5,    12, 0x0b090807, 0x080a0b07},
-	{1,  1350, 0, 5,     9, 0x08070605, 0x06070806},
-	{1,  1666, 0, 5,    11, 0x0a090806, 0x08090a06},
-	{1,  2140, 0, 4,    12, 0x0b090807, 0x080a0b07},
-	{}
-};
-
-static const struct board_specific_parameters *udimms[] = {
-	udimm0,
-};
-
-static const struct board_specific_parameters *rdimms[] = {
-	rdimm0,
-};
-#endif
diff --git a/board/freescale/t2080qds/eth_t2080qds.c b/board/freescale/t2080qds/eth_t2080qds.c
deleted file mode 100644
index 3e4ab8f..0000000
--- a/board/freescale/t2080qds/eth_t2080qds.c
+++ /dev/null
@@ -1,517 +0,0 @@
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * Shengzhou Liu <Shengzhou.Liu at freescale.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <netdev.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
-#include <asm/fsl_liodn.h>
-#include <malloc.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <miiphy.h>
-#include <phy.h>
-#include <asm/fsl_dtsec.h>
-#include <asm/fsl_serdes.h>
-#include "../common/qixis.h"
-#include "../common/fman.h"
-#include "t2080qds_qixis.h"
-
-#define EMI_NONE	0xFFFFFFFF
-#define EMI1_RGMII1	0
-#define EMI1_RGMII2     1
-#define EMI1_SLOT1	2
-#define EMI1_SLOT2	6
-#define EMI1_SLOT3	3
-#define EMI1_SLOT4	4
-#define EMI1_SLOT5	5
-#define EMI2		7
-
-static int mdio_mux[NUM_FM_PORTS];
-
-static const char * const mdio_names[] = {
-	"T2080QDS_MDIO_RGMII1",
-	"T2080QDS_MDIO_RGMII2",
-	"T2080QDS_MDIO_SLOT1",
-	"T2080QDS_MDIO_SLOT3",
-	"T2080QDS_MDIO_SLOT4",
-	"T2080QDS_MDIO_SLOT5",
-	"T2080QDS_MDIO_SLOT2",
-	"T2080QDS_MDIO_10GC",
-};
-
-/* Map SerDes1 8 lanes to default slot, will be initialized dynamically */
-static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1};
-
-static const char *T2080qds_mdio_name_for_muxval(u8 muxval)
-{
-	return mdio_names[muxval];
-}
-
-struct mii_dev *mii_dev_for_muxval(u8 muxval)
-{
-	struct mii_dev *bus;
-	const char *name = T2080qds_mdio_name_for_muxval(muxval);
-
-	if (!name) {
-		printf("No bus for muxval %x\n", muxval);
-		return NULL;
-	}
-
-	bus = miiphy_get_dev_by_name(name);
-
-	if (!bus) {
-		printf("No bus by name %s\n", name);
-		return NULL;
-	}
-
-	return bus;
-}
-
-struct T2080qds_mdio {
-	u8 muxval;
-	struct mii_dev *realbus;
-};
-
-static void T2080qds_mux_mdio(u8 muxval)
-{
-	u8 brdcfg4;
-	if (muxval < 7) {
-		brdcfg4 = QIXIS_READ(brdcfg[4]);
-		brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
-		brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
-		QIXIS_WRITE(brdcfg[4], brdcfg4);
-	}
-}
-
-static int T2080qds_mdio_read(struct mii_dev *bus, int addr, int devad,
-				int regnum)
-{
-	struct T2080qds_mdio *priv = bus->priv;
-
-	T2080qds_mux_mdio(priv->muxval);
-
-	return priv->realbus->read(priv->realbus, addr, devad, regnum);
-}
-
-static int T2080qds_mdio_write(struct mii_dev *bus, int addr, int devad,
-				int regnum, u16 value)
-{
-	struct T2080qds_mdio *priv = bus->priv;
-
-	T2080qds_mux_mdio(priv->muxval);
-
-	return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
-}
-
-static int T2080qds_mdio_reset(struct mii_dev *bus)
-{
-	struct T2080qds_mdio *priv = bus->priv;
-
-	return priv->realbus->reset(priv->realbus);
-}
-
-static int T2080qds_mdio_init(char *realbusname, u8 muxval)
-{
-	struct T2080qds_mdio *pmdio;
-	struct mii_dev *bus = mdio_alloc();
-
-	if (!bus) {
-		printf("Failed to allocate T2080QDS MDIO bus\n");
-		return -1;
-	}
-
-	pmdio = malloc(sizeof(*pmdio));
-	if (!pmdio) {
-		printf("Failed to allocate T2080QDS private data\n");
-		free(bus);
-		return -1;
-	}
-
-	bus->read = T2080qds_mdio_read;
-	bus->write = T2080qds_mdio_write;
-	bus->reset = T2080qds_mdio_reset;
-	sprintf(bus->name, T2080qds_mdio_name_for_muxval(muxval));
-
-	pmdio->realbus = miiphy_get_dev_by_name(realbusname);
-
-	if (!pmdio->realbus) {
-		printf("No bus with name %s\n", realbusname);
-		free(bus);
-		free(pmdio);
-		return -1;
-	}
-
-	pmdio->muxval = muxval;
-	bus->priv = pmdio;
-
-	return mdio_register(bus);
-}
-
-void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
-				enum fm_port port, int offset)
-{
-	int phy;
-	char alias[20];
-	struct fixed_link f_link;
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
-				FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
-
-	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
-	if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
-		phy = fm_info_get_phy_address(port);
-		switch (port) {
-		case FM1_DTSEC1:
-		case FM1_DTSEC2:
-		case FM1_DTSEC9:
-		case FM1_DTSEC10:
-			sprintf(alias, "phy_sgmii_s3_%x", phy);
-			fdt_set_phy_handle(fdt, compat, addr, alias);
-			fdt_status_okay_by_alias(fdt, "emi1_slot3");
-			break;
-		case FM1_DTSEC5:
-		case FM1_DTSEC6:
-			if (mdio_mux[port] == EMI1_SLOT1) {
-				sprintf(alias, "phy_sgmii_s1_%x", phy);
-				fdt_set_phy_handle(fdt, compat, addr, alias);
-				fdt_status_okay_by_alias(fdt, "emi1_slot1");
-			} else if (mdio_mux[port] == EMI1_SLOT2) {
-				sprintf(alias, "phy_sgmii_s2_%x", phy);
-				fdt_set_phy_handle(fdt, compat, addr, alias);
-				fdt_status_okay_by_alias(fdt, "emi1_slot2");
-			}
-			break;
-		default:
-			break;
-		}
-
-	} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
-		switch (srds_s1) {
-		case 0x66: /* XFI interface */
-		case 0x6b:
-		case 0x6c:
-		case 0x6d:
-		case 0x71:
-			f_link.phy_id = port;
-			f_link.duplex = 1;
-			f_link.link_speed = 10000;
-			f_link.pause = 0;
-			f_link.asym_pause = 0;
-			/* no PHY for XFI */
-			fdt_delprop(fdt, offset, "phy-handle");
-			fdt_setprop(fdt, offset, "fixed-link", &f_link,
-				    sizeof(f_link));
-			break;
-		default:
-			break;
-		}
-	}
-}
-
-void fdt_fixup_board_enet(void *fdt)
-{
-	return;
-}
-
-/*
- * This function reads RCW to check if Serdes1{E,F,G,H} is configured
- * as slot 1/2/3 and update the lane_to_slot[] array accordingly
- */
-static void initialize_lane_to_slot(void)
-{
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
-				FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
-
-	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
-	switch (srds_s1) {
-	case 0x51:
-	case 0x5f:
-	case 0x65:
-	case 0x6b:
-	case 0x71:
-		lane_to_slot[5] = 2;
-		lane_to_slot[6] = 2;
-		lane_to_slot[7] = 2;
-		break;
-	case 0xa6:
-	case 0x8e:
-	case 0x8f:
-	case 0x82:
-	case 0x83:
-	case 0xd3:
-	case 0xd9:
-	case 0xcb:
-		lane_to_slot[6] = 2;
-		lane_to_slot[7] = 2;
-		break;
-	case 0xda:
-		lane_to_slot[4] = 3;
-		lane_to_slot[5] = 3;
-		lane_to_slot[6] = 3;
-		lane_to_slot[7] = 3;
-		break;
-	default:
-		break;
-	}
-}
-
-int board_eth_init(bd_t *bis)
-{
-#if defined(CONFIG_FMAN_ENET)
-	int i, idx, lane, slot, interface;
-	struct memac_mdio_info dtsec_mdio_info;
-	struct memac_mdio_info tgec_mdio_info;
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
-	u32 srds_s1;
-
-	srds_s1 = in_be32(&gur->rcwsr[4]) &
-					FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
-	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
-	initialize_lane_to_slot();
-
-	/* Initialize the mdio_mux array so we can recognize empty elements */
-	for (i = 0; i < NUM_FM_PORTS; i++)
-		mdio_mux[i] = EMI_NONE;
-
-	dtsec_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
-
-	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
-	/* Register the 1G MDIO bus */
-	fm_memac_mdio_init(bis, &dtsec_mdio_info);
-
-	tgec_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
-	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
-
-	/* Register the 10G MDIO bus */
-	fm_memac_mdio_init(bis, &tgec_mdio_info);
-
-	/* Register the muxing front-ends to the MDIO buses */
-	T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
-	T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
-	T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
-	T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
-	T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
-	T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
-	T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
-	T2080qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
-
-	/* Set the two on-board RGMII PHY address */
-	fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
-	if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
-			FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII)
-		fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
-	else
-		fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR);
-
-	switch (srds_s1) {
-	case 0x1c:
-	case 0x95:
-	case 0xa2:
-	case 0x94:
-		/* SGMII in Slot3 */
-		fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
-		/* SGMII in Slot2 */
-		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
-		break;
-	case 0x51:
-	case 0x5f:
-	case 0x65:
-		/* XAUI/HiGig in Slot3 */
-		fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
-		/* SGMII in Slot2 */
-		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
-		break;
-	case 0x66:
-		/*
-		 * XFI does not need a PHY to work, but to avoid U-boot use
-		 * default PHY address which is zero to a MAC when it found
-		 * a MAC has no PHY address, we give a PHY address to XFI
-		 * MAC, and should not use a real XAUI PHY address, since
-		 * MDIO can access it successfully, and then MDIO thinks
-		 * the XAUI card is used for the XFI MAC, which will cause
-		 * error.
-		 */
-		fm_info_set_phy_address(FM1_10GEC1, 4);
-		fm_info_set_phy_address(FM1_10GEC2, 5);
-		fm_info_set_phy_address(FM1_10GEC3, 6);
-		fm_info_set_phy_address(FM1_10GEC4, 7);
-		break;
-	case 0x6b:
-		fm_info_set_phy_address(FM1_10GEC1, 4);
-		fm_info_set_phy_address(FM1_10GEC2, 5);
-		fm_info_set_phy_address(FM1_10GEC3, 6);
-		fm_info_set_phy_address(FM1_10GEC4, 7);
-		/* SGMII in Slot2 */
-		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
-		break;
-	case 0x6c:
-	case 0x6d:
-		fm_info_set_phy_address(FM1_10GEC1, 4);
-		fm_info_set_phy_address(FM1_10GEC2, 5);
-		/* SGMII in Slot3 */
-		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
-		break;
-	case 0x71:
-		/* SGMII in Slot3 */
-		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
-		/* SGMII in Slot2 */
-		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
-		break;
-	case 0xa6:
-	case 0x8e:
-	case 0x8f:
-	case 0x82:
-	case 0x83:
-		/* SGMII in Slot3 */
-		fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
-		/* SGMII in Slot2 */
-		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
-		break;
-	case 0xa4:
-	case 0x96:
-	case 0x8a:
-		/* SGMII in Slot3 */
-		fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
-		break;
-	case 0xd9:
-	case 0xd3:
-	case 0xcb:
-		/* SGMII in Slot3 */
-		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
-		/* SGMII in Slot2 */
-		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
-		break;
-	default:
-		break;
-	}
-
-	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
-		idx = i - FM1_DTSEC1;
-		interface = fm_info_get_enet_if(i);
-		switch (interface) {
-		case PHY_INTERFACE_MODE_SGMII:
-			lane = serdes_get_first_lane(FSL_SRDS_1,
-					SGMII_FM1_DTSEC1 + idx);
-			if (lane < 0)
-				break;
-			slot = lane_to_slot[lane];
-			debug("FM1 at DTSEC%u expects SGMII in slot %u\n",
-			      idx + 1, slot);
-			if (QIXIS_READ(present2) & (1 << (slot - 1)))
-				fm_disable_port(i);
-
-			switch (slot) {
-			case 1:
-				mdio_mux[i] = EMI1_SLOT1;
-				fm_info_set_mdio(i, mii_dev_for_muxval(
-						 mdio_mux[i]));
-				break;
-			case 2:
-				mdio_mux[i] = EMI1_SLOT2;
-				fm_info_set_mdio(i, mii_dev_for_muxval(
-						 mdio_mux[i]));
-				break;
-			case 3:
-				mdio_mux[i] = EMI1_SLOT3;
-				fm_info_set_mdio(i, mii_dev_for_muxval(
-						mdio_mux[i]));
-				break;
-			}
-			break;
-		case PHY_INTERFACE_MODE_RGMII:
-			if (i == FM1_DTSEC3)
-				mdio_mux[i] = EMI1_RGMII1;
-			else if (i == FM1_DTSEC4 || FM1_DTSEC10)
-				mdio_mux[i] = EMI1_RGMII2;
-			fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
-			break;
-		default:
-			break;
-		}
-	}
-
-	for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
-		idx = i - FM1_10GEC1;
-		switch (fm_info_get_enet_if(i)) {
-		case PHY_INTERFACE_MODE_XGMII:
-			if (srds_s1 == 0x51) {
-				lane = serdes_get_first_lane(FSL_SRDS_1,
-						XAUI_FM1_MAC9 + idx);
-			} else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) {
-				lane = serdes_get_first_lane(FSL_SRDS_1,
-						HIGIG_FM1_MAC9 + idx);
-			} else {
-				if (i == FM1_10GEC1 || i == FM1_10GEC2)
-					lane = serdes_get_first_lane(FSL_SRDS_1,
-						XFI_FM1_MAC9 + idx);
-				else
-					lane = serdes_get_first_lane(FSL_SRDS_1,
-						XFI_FM1_MAC1 + idx);
-			}
-
-			if (lane < 0)
-				break;
-			mdio_mux[i] = EMI2;
-			fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
-
-			if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) ||
-			    (srds_s1 == 0x6c) || (srds_s1 == 0x6d) ||
-			    (srds_s1 == 0x71)) {
-				/* As XFI is in cage intead of a slot, so
-				 * ensure doesn't disable the corresponding port
-				 */
-				break;
-			}
-
-			slot = lane_to_slot[lane];
-			if (QIXIS_READ(present2) & (1 << (slot - 1)))
-				fm_disable_port(i);
-			break;
-		default:
-			break;
-		}
-	}
-
-	cpu_eth_init(bis);
-#endif /* CONFIG_FMAN_ENET */
-
-	return pci_eth_init(bis);
-}
diff --git a/board/freescale/t2080qds/law.c b/board/freescale/t2080qds/law.c
deleted file mode 100644
index 74e2a53..0000000
--- a/board/freescale/t2080qds/law.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright 2008-2012 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
-#endif
-#ifdef QIXIS_BASE_PHYS
-	SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-	/* Limit DCSR to 32M to access NPC Trace Buffer */
-	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/t2080qds/pci.c b/board/freescale/t2080qds/pci.c
deleted file mode 100644
index 84a89da..0000000
--- a/board/freescale/t2080qds/pci.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright 2007-2013 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-
-void pci_init_board(void)
-{
-	fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, bd_t *bd)
-{
-	FT_FSL_PCI_SETUP;
-}
diff --git a/board/freescale/t2080qds/t2080_pbi.cfg b/board/freescale/t2080qds/t2080_pbi.cfg
deleted file mode 100644
index e200d92..0000000
--- a/board/freescale/t2080qds/t2080_pbi.cfg
+++ /dev/null
@@ -1,41 +0,0 @@
-#
-# Copyright 2013 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier:      GPL-2.0+
-#
-# Refer doc/README.pblimage for more details about how-to configure
-# and create PBL boot image
-#
-
-#PBI commands
-#Initialize CPC1
-09010000 00200400
-09138000 00000000
-091380c0 00000100
-#512KB SRAM
-09010100 00000000
-09010104 fff80009
-09010f00 08000000
-#enable CPC1
-09010000 80000000
-#Configure LAW for CPC1
-09000d00 00000000
-09000d04 fff80000
-09000d08 81000012
-#Initialize eSPI controller, default configuration is slow for eSPI to
-#load data, this configuration comes from u-boot eSPI driver.
-09110000 80000403
-09110020 2d170008
-09110024 00100008
-09110028 00100008
-0911002c 00100008
-#Errata for slowing down the MDC clock to make it <= 2.5 MHZ
-094fc030 00008148
-094fd030 00008148
-#Configure alternate space
-09000010 00000000
-09000014 ff000000
-09000018 81000000
-#Flush PBL data
-09138000 00000000
-091380c0 00000000
diff --git a/board/freescale/t2080qds/t2080_rcw.cfg b/board/freescale/t2080qds/t2080_rcw.cfg
deleted file mode 100644
index c2ad0fd..0000000
--- a/board/freescale/t2080qds/t2080_rcw.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-#SerDes Protocol: 0x66_0x16
-#Core/DDR: 1533Mhz/2133MT/s
-12100017 15000000 00000000 00000000
-66160002 00008400 e8104000 c1000000
-00000000 00000000 00000000 000307fc
-00000000 00000000 00000000 00000004
diff --git a/board/freescale/t2080qds/t2080qds.c b/board/freescale/t2080qds/t2080qds.c
deleted file mode 100644
index 4fe8ccb..0000000
--- a/board/freescale/t2080qds/t2080qds.c
+++ /dev/null
@@ -1,378 +0,0 @@
-/*
- * Copyright 2009-2013 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <i2c.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
-#include <asm/fsl_liodn.h>
-#include <fm_eth.h>
-
-#include "../common/qixis.h"
-#include "../common/vsc3316_3308.h"
-#include "t2080qds.h"
-#include "t2080qds_qixis.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	char buf[64];
-	u8 sw;
-	struct cpu_type *cpu = gd->arch.cpu;
-	static const char *freq[4] = {
-		"100.00MHZ(from 8T49N222A)", "125.00MHz",
-		"156.25MHZ", "100.00MHz"
-	};
-
-	printf("Board: %sQDS, ", cpu->name);
-	sw = QIXIS_READ(arch);
-	printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
-	printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
-
-#ifdef CONFIG_SDCARD
-	puts("SD/MMC\n");
-#elif CONFIG_SPIFLASH
-	puts("SPI\n");
-#else
-	sw = QIXIS_READ(brdcfg[0]);
-	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
-
-	if (sw < 0x8)
-		printf("vBank%d\n", sw);
-	else if (sw == 0x8)
-		puts("Promjet\n");
-	else if (sw == 0x9)
-		puts("NAND\n");
-	else
-		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
-#endif
-
-	printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver),
-	       qixis_read_tag(buf), (int)qixis_read_minor());
-	/* the timestamp string contains "\n" at the end */
-	printf(" on %s", qixis_read_time(buf));
-
-	puts("SERDES Reference Clocks:\n");
-	sw = QIXIS_READ(brdcfg[2]);
-	printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6],
-	       freq[(sw >> 4) & 0x3]);
-	printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2],
-	       freq[sw & 0x3]);
-
-	return 0;
-}
-
-int select_i2c_ch_pca9547(u8 ch)
-{
-	int ret;
-
-	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
-	if (ret) {
-		puts("PCA: failed to select proper channel\n");
-		return ret;
-	}
-
-	return 0;
-}
-
-int brd_mux_lane_to_slot(void)
-{
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	u32 srds_prtcl_s1, srds_prtcl_s2;
-
-	srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
-				FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
-	srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-	srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
-				FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
-	srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
-
-	switch (srds_prtcl_s1) {
-	case 0:
-		/* SerDes1 is not enabled */
-		break;
-	case 0x1c:
-	case 0xa2:
-		/* SD1(A:D) => SLOT3 SGMII
-		 * SD1(G:H) => SLOT1 SGMII
-		 */
-		QIXIS_WRITE(brdcfg[12], 0x1a);
-		break;
-	case 0x94:
-	case 0x95:
-		/* SD1(A:B) => SLOT3 SGMII at 1.25bps
-		 * SD1(C:D) => SFP Module, SGMII at 3.125bps
-		 * SD1(E:H) => SLOT1 SGMII at 1.25bps
-		 */
-	case 0x96:
-		/* SD1(A:B) => SLOT3 SGMII at 1.25bps
-		 * SD1(C)   => SFP Module, SGMII at 3.125bps
-		 * SD1(D)   => SFP Module, SGMII at 1.25bps
-		 * SD1(E:H) => SLOT1 PCIe4 x4
-		 */
-		QIXIS_WRITE(brdcfg[12], 0x3a);
-		break;
-	case 0x51:
-		/* SD1(A:D) => SLOT3 XAUI
-		 * SD1(E)   => SLOT1 PCIe4
-		 * SD1(F:H) => SLOT2 SGMII
-		 */
-		QIXIS_WRITE(brdcfg[12], 0x15);
-		break;
-	case 0x66:
-	case 0x67:
-		/* SD1(A:D) => XFI cage
-		 * SD1(E:H) => SLOT1 PCIe4
-		 */
-		QIXIS_WRITE(brdcfg[12], 0xfe);
-		break;
-	case 0x6b:
-		/* SD1(A:D) => XFI cage
-		 * SD1(E)   => SLOT1 PCIe4
-		 * SD1(F:H) => SLOT2 SGMII
-		 */
-		QIXIS_WRITE(brdcfg[12], 0xf1);
-		break;
-	case 0x6c:
-	case 0x6d:
-		/* SD1(A:B) => XFI cage
-		 * SD1(C:D) => SLOT3 SGMII
-		 * SD1(E:H) => SLOT1 PCIe4
-		 */
-		QIXIS_WRITE(brdcfg[12], 0xda);
-		break;
-	case 0x6e:
-		/* SD1(A:B) => SFP Module, XFI
-		 * SD1(C:D) => SLOT3 SGMII
-		 * SD1(E:F) => SLOT1 PCIe4 x2
-		 * SD1(G:H) => SLOT2 SGMII
-		 */
-		QIXIS_WRITE(brdcfg[12], 0xd9);
-		break;
-	case 0xda:
-		/* SD1(A:H) => SLOT3 PCIe3 x8
-		 */
-		 QIXIS_WRITE(brdcfg[12], 0x0);
-		 break;
-	case 0xc8:
-		/* SD1(A)   => SLOT3 PCIe3 x1
-		 * SD1(B)   => SFP Module, SGMII at 1.25bps
-		 * SD1(C:D) => SFP Module, SGMII at 3.125bps
-		 * SD1(E:F) => SLOT1 PCIe4 x2
-		 * SD1(G:H) => SLOT2 SGMII
-		 */
-		 QIXIS_WRITE(brdcfg[12], 0x79);
-		 break;
-	case 0xab:
-		/* SD1(A:D) => SLOT3 PCIe3 x4
-		 * SD1(E:H) => SLOT1 PCIe4 x4
-		 */
-		 QIXIS_WRITE(brdcfg[12], 0x1a);
-		 break;
-	default:
-		printf("WARNING: unsupported for SerDes1 Protocol %d\n",
-		       srds_prtcl_s1);
-		return -1;
-	}
-
-	switch (srds_prtcl_s2) {
-	case 0:
-		/* SerDes2 is not enabled */
-		break;
-	case 0x01:
-	case 0x02:
-		/* SD2(A:H) => SLOT4 PCIe1 */
-		QIXIS_WRITE(brdcfg[13], 0x10);
-		break;
-	case 0x15:
-	case 0x16:
-		/*
-		 * SD2(A:D) => SLOT4 PCIe1
-		 * SD2(E:F) => SLOT5 PCIe2
-		 * SD2(G:H) => SATA1,SATA2
-		 */
-		QIXIS_WRITE(brdcfg[13], 0xb0);
-		break;
-	case 0x18:
-		/*
-		 * SD2(A:D) => SLOT4 PCIe1
-		 * SD2(E:F) => SLOT5 Aurora
-		 * SD2(G:H) => SATA1,SATA2
-		 */
-		QIXIS_WRITE(brdcfg[13], 0x78);
-		break;
-	case 0x1f:
-		/*
-		 * SD2(A:D) => SLOT4 PCIe1
-		 * SD2(E:H) => SLOT5 PCIe2
-		 */
-		QIXIS_WRITE(brdcfg[13], 0xa0);
-		break;
-	case 0x29:
-	case 0x2d:
-	case 0x2e:
-		/*
-		 * SD2(A:D) => SLOT4 SRIO2
-		 * SD2(E:H) => SLOT5 SRIO1
-		 */
-		QIXIS_WRITE(brdcfg[13], 0xa0);
-		break;
-	case 0x36:
-		/*
-		 * SD2(A:D) => SLOT4 SRIO2
-		 * SD2(E:F) => Aurora
-		 * SD2(G:H) => SATA1,SATA2
-		 */
-		QIXIS_WRITE(brdcfg[13], 0x78);
-		break;
-	default:
-		printf("WARNING: unsupported for SerDes2 Protocol %d\n",
-		       srds_prtcl_s2);
-		return -1;
-	}
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
-	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
-
-	/*
-	 * Remap Boot flash + PROMJET region to caching-inhibited
-	 * so that flash can be erased properly.
-	 */
-
-	/* Flush d-cache and invalidate i-cache of any FLASH data */
-	flush_dcache();
-	invalidate_icache();
-
-	/* invalidate existing TLB entry for flash + promjet */
-	disable_tlb(flash_esel);
-
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, flash_esel, BOOKE_PAGESZ_256M, 1);
-
-	set_liodns();
-#ifdef CONFIG_SYS_DPAA_QBMAN
-	setup_portals();
-#endif
-
-	/* Disable remote I2C connection to qixis fpga */
-	QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
-
-	brd_mux_lane_to_slot();
-	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
-
-	return 0;
-}
-
-unsigned long get_board_sys_clk(void)
-{
-	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
-#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
-	/* use accurate clock measurement */
-	int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
-	int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
-	u32 val;
-
-	val =  freq * base;
-	if (val) {
-		debug("SYS Clock measurement is: %d\n", val);
-		return val;
-	} else {
-		printf("Warning: SYS clock measurement is invalid, ");
-		printf("using value from brdcfg1.\n");
-	}
-#endif
-
-	switch (sysclk_conf & 0x0F) {
-	case QIXIS_SYSCLK_83:
-		return 83333333;
-	case QIXIS_SYSCLK_100:
-		return 100000000;
-	case QIXIS_SYSCLK_125:
-		return 125000000;
-	case QIXIS_SYSCLK_133:
-		return 133333333;
-	case QIXIS_SYSCLK_150:
-		return 150000000;
-	case QIXIS_SYSCLK_160:
-		return 160000000;
-	case QIXIS_SYSCLK_166:
-		return 166666666;
-	}
-	return 66666666;
-}
-
-unsigned long get_board_ddr_clk(void)
-{
-	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
-#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
-	/* use accurate clock measurement */
-	int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
-	int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
-	u32 val;
-
-	val =  freq * base;
-	if (val) {
-		debug("DDR Clock measurement is: %d\n", val);
-		return val;
-	} else {
-		printf("Warning: DDR clock measurement is invalid, ");
-		printf("using value from brdcfg1.\n");
-	}
-#endif
-
-	switch ((ddrclk_conf & 0x30) >> 4) {
-	case QIXIS_DDRCLK_100:
-		return 100000000;
-	case QIXIS_DDRCLK_125:
-		return 125000000;
-	case QIXIS_DDRCLK_133:
-		return 133333333;
-	}
-	return 66666666;
-}
-
-int misc_init_r(void)
-{
-	return 0;
-}
-
-void ft_board_setup(void *blob, bd_t *bd)
-{
-	phys_addr_t base;
-	phys_size_t size;
-
-	ft_cpu_setup(blob, bd);
-
-	base = getenv_bootm_low();
-	size = getenv_bootm_size();
-
-	fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_PCI
-	pci_of_setup(blob, bd);
-#endif
-
-	fdt_fixup_liodn(blob);
-	fdt_fixup_dr_usb(blob, bd);
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-	fdt_fixup_fman_ethernet(blob);
-	fdt_fixup_board_enet(blob);
-#endif
-}
diff --git a/board/freescale/t2080qds/t2080qds.h b/board/freescale/t2080qds/t2080qds.h
deleted file mode 100644
index 39fcef2..0000000
--- a/board/freescale/t2080qds/t2080qds.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright 2011-2013 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CORENET_DS_H__
-#define __CORENET_DS_H__
-
-void fdt_fixup_board_enet(void *blob);
-void pci_of_setup(void *blob, bd_t *bd);
-
-#endif
diff --git a/board/freescale/t2080qds/t2080qds_qixis.h b/board/freescale/t2080qds/t2080qds_qixis.h
deleted file mode 100644
index fc83da7..0000000
--- a/board/freescale/t2080qds/t2080qds_qixis.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#ifndef __T2080QDS_QIXIS_H__
-#define __T2080QDS_QIXIS_H__
-
-/* Definitions of QIXIS Registers for T2080QDS */
-
-#define QIXIS_SRDS1CLK_122		0x5a
-#define QIXIS_SRDS1CLK_125		0x5e
-
-
-/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
-#define BRDCFG4_EMISEL_MASK             0xE0
-#define BRDCFG4_EMISEL_SHIFT            5
-
-/* SYSCLK */
-#define QIXIS_SYSCLK_66                 0x0
-#define QIXIS_SYSCLK_83                 0x1
-#define QIXIS_SYSCLK_100                0x2
-#define QIXIS_SYSCLK_125                0x3
-#define QIXIS_SYSCLK_133                0x4
-#define QIXIS_SYSCLK_150                0x5
-#define QIXIS_SYSCLK_160                0x6
-#define QIXIS_SYSCLK_166                0x7
-
-/* DDRCLK */
-#define QIXIS_DDRCLK_66                 0x0
-#define QIXIS_DDRCLK_100                0x1
-#define QIXIS_DDRCLK_125                0x2
-#define QIXIS_DDRCLK_133                0x3
-
-#define BRDCFG5_IRE                     0x20    /* i2c Remote i2c1 enable */
-
-#define BRDCFG12_SD3EN_MASK             0x20
-#define BRDCFG12_SD3MX_MASK             0x08
-#define BRDCFG12_SD3MX_SLOT5            0x08
-#define BRDCFG12_SD3MX_SLOT6            0x00
-#define BRDCFG12_SD4EN_MASK             0x04
-#define BRDCFG12_SD4MX_MASK             0x03
-#define BRDCFG12_SD4MX_SLOT7            0x02
-#define BRDCFG12_SD4MX_SLOT8            0x01
-#define BRDCFG12_SD4MX_AURO_SATA        0x00
-#endif
diff --git a/board/freescale/t2080qds/tlb.c b/board/freescale/t2080qds/tlb.c
deleted file mode 100644
index 62cd110..0000000
--- a/board/freescale/t2080qds/tlb.c
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * Copyright 2008-2013 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-
-	/* TLB 1 */
-	/* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
-	/*
-	 * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
-	 * SRAM is at 0xfff00000, it covered the 0xfffff000.
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_1M, 1),
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-	/*
-	 * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
-	 * space is at 0xfff00000, it covered the 0xfffff000.
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
-		      CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_1M, 1),
-#else
-	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_4K, 1),
-#endif
-
-	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 1, BOOKE_PAGESZ_16M, 1),
-
-	/* *I*G* - Flash, localbus */
-	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
-		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
-		      0, 2, BOOKE_PAGESZ_256M, 1),
-
-	/* *I*G* - PCIe 1, 0x80000000 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 3, BOOKE_PAGESZ_512M, 1),
-
-	/* *I*G* - PCIe 2, 0xa0000000 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 4, BOOKE_PAGESZ_256M, 1),
-
-	/* *I*G* - PCIe 3, 0xb0000000 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 5, BOOKE_PAGESZ_256M, 1),
-
-
-	/* *I*G* - PCIe 4, 0xc0000000 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 6, BOOKE_PAGESZ_256M, 1),
-
-	/* *I*G* - PCI I/O */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 7, BOOKE_PAGESZ_256K, 1),
-
-	/* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 9, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 10, BOOKE_PAGESZ_16M, 1),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 11, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 12, BOOKE_PAGESZ_16M, 1),
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 13, BOOKE_PAGESZ_32M, 1),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE
-	/*
-	 * *I*G - NAND
-	 * entry 14 and 15 has been used hard coded, they will be disabled
-	 * in cpu_init_f, so we use entry 16 for nand.
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 16, BOOKE_PAGESZ_64K, 1),
-#endif
-#ifdef QIXIS_BASE_PHYS
-	SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 17, BOOKE_PAGESZ_4K, 1),
-#endif
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-	/*
-	 * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
-	 * fetching ucode and ENV from master
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
-		      CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
-		      0, 18, BOOKE_PAGESZ_1M, 1),
-#endif
-
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/t208xqds/Makefile b/board/freescale/t208xqds/Makefile
new file mode 100644
index 0000000..947b7f7
--- /dev/null
+++ b/board/freescale/t208xqds/Makefile
@@ -0,0 +1,14 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-$(CONFIG_T2080QDS) += t208xqds.o
+obj-$(CONFIG_T2080QDS) += eth_t208xqds.o
+obj-$(CONFIG_T2081QDS) += t208xqds.o
+obj-$(CONFIG_T2081QDS) += eth_t208xqds.o
+obj-$(CONFIG_PCI)      += pci.o
+obj-y   += ddr.o
+obj-y   += law.o
+obj-y   += tlb.o
diff --git a/board/freescale/t208xqds/ddr.c b/board/freescale/t208xqds/ddr.c
new file mode 100644
index 0000000..ed1334d
--- /dev/null
+++ b/board/freescale/t208xqds/ddr.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 or later as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+	ulong ddr_freq;
+
+	if (ctrl_num > 1) {
+		printf("Not supported controller number %d\n", ctrl_num);
+		return;
+	}
+	if (!pdimm->n_ranks)
+		return;
+
+	/*
+	 * we use identical timing for all slots. If needed, change the code
+	 * to  pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
+	 */
+	if (popts->registered_dimm_en)
+		pbsp = rdimms[0];
+	else
+		pbsp = udimms[0];
+
+	/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(0) / 1000000;
+	while (pbsp->datarate_mhz_high) {
+		if (pbsp->n_ranks == pdimm->n_ranks &&
+		    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
+			if (ddr_freq <= pbsp->datarate_mhz_high) {
+				popts->clk_adjust = pbsp->clk_adjust;
+				popts->wrlvl_start = pbsp->wrlvl_start;
+				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+				goto found;
+			}
+			pbsp_highest = pbsp;
+		}
+		pbsp++;
+	}
+
+	if (pbsp_highest) {
+		printf("Error: board specific timing not found");
+		printf("for data rate %lu MT/s\n", ddr_freq);
+		printf("Trying to use the highest speed (%u) parameters\n",
+		       pbsp_highest->datarate_mhz_high);
+		popts->clk_adjust = pbsp_highest->clk_adjust;
+		popts->wrlvl_start = pbsp_highest->wrlvl_start;
+		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+	} else {
+		panic("DIMM is not supported by this board");
+	}
+found:
+	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+		"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
+		"wrlvl_ctrl_3 0x%x\n",
+		pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+		pbsp->wrlvl_ctl_3);
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+	/*
+	 * Write leveling override
+	 */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+
+	/*
+	 * Rtt and Rtt_WR override
+	 */
+	popts->rtt_override = 0;
+
+	/* Enable ZQ calibration */
+	popts->zq_en = 1;
+
+	/* DHC_EN =1, ODT = 75 Ohm */
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+}
+
+phys_size_t initdram(int board_type)
+{
+	phys_size_t dram_size;
+
+	puts("Initializing....using SPD\n");
+
+	dram_size = fsl_ddr_sdram();
+
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+
+	puts("    DDR: ");
+	return dram_size;
+}
diff --git a/board/freescale/t208xqds/ddr.h b/board/freescale/t208xqds/ddr.h
new file mode 100644
index 0000000..9fc879a
--- /dev/null
+++ b/board/freescale/t208xqds/ddr.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+	u32 n_ranks;
+	u32 datarate_mhz_high;
+	u32 rank_gb;
+	u32 clk_adjust;
+	u32 wrlvl_start;
+	u32 wrlvl_ctl_2;
+	u32 wrlvl_ctl_3;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+
+static const struct board_specific_parameters udimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl |
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
+	 */
+	{2,  1200, 2, 5,     7, 0x0808090a, 0x0b0c0c0a},
+	{2,  1500, 2, 5,     6, 0x07070809, 0x0a0b0b09},
+	{2,  1600, 2, 5,     8, 0x090b0b0d, 0x0d0e0f0b},
+	{2,  1700, 2, 4,     7, 0x080a0a0c, 0x0c0d0e0a},
+	{2,  1900, 2, 5,     9, 0x0a0b0c0e, 0x0f10120c},
+	{2,  2140, 2, 4,     8, 0x090a0b0d, 0x0e0f110b},
+	{1,  1200, 2, 5,     7, 0x0808090a, 0x0b0c0c0a},
+	{1,  1500, 2, 5,     6, 0x07070809, 0x0a0b0b09},
+	{1,  1600, 2, 5,     8, 0x090b0b0d, 0x0d0e0f0b},
+	{1,  1700, 2, 4,     7, 0x080a0a0c, 0x0c0d0e0a},
+	{1,  1900, 2, 5,     9, 0x0a0b0c0e, 0x0f10120c},
+	{1,  2140, 2, 4,     8, 0x090a0b0d, 0x0e0f110b},
+	{}
+};
+
+static const struct board_specific_parameters rdimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl |
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
+	 */
+	/* TODO: need tuning these parameters if RDIMM is used */
+	{4,  1350, 0, 5,     9, 0x08070605, 0x06070806},
+	{4,  1666, 0, 5,    11, 0x0a080706, 0x07090906},
+	{4,  2140, 0, 5,    12, 0x0b090807, 0x080a0b07},
+	{2,  1350, 0, 5,     9, 0x08070605, 0x06070806},
+	{2,  1666, 0, 5,    11, 0x0a090806, 0x08090a06},
+	{2,  2140, 0, 5,    12, 0x0b090807, 0x080a0b07},
+	{1,  1350, 0, 5,     9, 0x08070605, 0x06070806},
+	{1,  1666, 0, 5,    11, 0x0a090806, 0x08090a06},
+	{1,  2140, 0, 4,    12, 0x0b090807, 0x080a0b07},
+	{}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+	udimm0,
+};
+
+static const struct board_specific_parameters *rdimms[] = {
+	rdimm0,
+};
+#endif
diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c
new file mode 100644
index 0000000..7d8411b
--- /dev/null
+++ b/board/freescale/t208xqds/eth_t208xqds.c
@@ -0,0 +1,648 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Shengzhou Liu <Shengzhou.Liu at freescale.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <malloc.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <asm/fsl_dtsec.h>
+#include <asm/fsl_serdes.h>
+#include "../common/qixis.h"
+#include "../common/fman.h"
+#include "t208xqds_qixis.h"
+
+#define EMI_NONE	0xFFFFFFFF
+#define EMI1_RGMII1	0
+#define EMI1_RGMII2     1
+#define EMI1_SLOT1	2
+#if defined(CONFIG_T2080QDS)
+#define EMI1_SLOT2	6
+#define EMI1_SLOT3	3
+#define EMI1_SLOT4	4
+#define EMI1_SLOT5	5
+#elif defined(CONFIG_T2081QDS)
+#define EMI1_SLOT2      3
+#define EMI1_SLOT3      4
+#define EMI1_SLOT5      5
+#define EMI1_SLOT6      6
+#define EMI1_SLOT7      7
+#endif
+#define EMI2		8
+
+static int mdio_mux[NUM_FM_PORTS];
+
+static const char * const mdio_names[] = {
+#if defined(CONFIG_T2080QDS)
+	"T2080QDS_MDIO_RGMII1",
+	"T2080QDS_MDIO_RGMII2",
+	"T2080QDS_MDIO_SLOT1",
+	"T2080QDS_MDIO_SLOT3",
+	"T2080QDS_MDIO_SLOT4",
+	"T2080QDS_MDIO_SLOT5",
+	"T2080QDS_MDIO_SLOT2",
+	"T2080QDS_MDIO_10GC",
+#elif defined(CONFIG_T2081QDS)
+	"T2081QDS_MDIO_RGMII1",
+	"T2081QDS_MDIO_RGMII2",
+	"T2081QDS_MDIO_SLOT1",
+	"T2081QDS_MDIO_SLOT2",
+	"T2081QDS_MDIO_SLOT3",
+	"T2081QDS_MDIO_SLOT5",
+	"T2081QDS_MDIO_SLOT6",
+	"T2081QDS_MDIO_SLOT7",
+	"T2081QDS_MDIO_10GC",
+#endif
+};
+
+/* Map SerDes1 8 lanes to default slot, will be initialized dynamically */
+#if defined(CONFIG_T2080QDS)
+static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1};
+#elif defined(CONFIG_T2081QDS)
+static u8 lane_to_slot[] = {2, 2, 2, 2, 1, 1, 1, 1};
+#endif
+
+static const char *t208xqds_mdio_name_for_muxval(u8 muxval)
+{
+	return mdio_names[muxval];
+}
+
+struct mii_dev *mii_dev_for_muxval(u8 muxval)
+{
+	struct mii_dev *bus;
+	const char *name = t208xqds_mdio_name_for_muxval(muxval);
+
+	if (!name) {
+		printf("No bus for muxval %x\n", muxval);
+		return NULL;
+	}
+
+	bus = miiphy_get_dev_by_name(name);
+
+	if (!bus) {
+		printf("No bus by name %s\n", name);
+		return NULL;
+	}
+
+	return bus;
+}
+
+struct t208xqds_mdio {
+	u8 muxval;
+	struct mii_dev *realbus;
+};
+
+static void t208xqds_mux_mdio(u8 muxval)
+{
+	u8 brdcfg4;
+	if (muxval < 8) {
+		brdcfg4 = QIXIS_READ(brdcfg[4]);
+		brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
+		brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
+		QIXIS_WRITE(brdcfg[4], brdcfg4);
+	}
+}
+
+static int t208xqds_mdio_read(struct mii_dev *bus, int addr, int devad,
+				int regnum)
+{
+	struct t208xqds_mdio *priv = bus->priv;
+
+	t208xqds_mux_mdio(priv->muxval);
+
+	return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int t208xqds_mdio_write(struct mii_dev *bus, int addr, int devad,
+				int regnum, u16 value)
+{
+	struct t208xqds_mdio *priv = bus->priv;
+
+	t208xqds_mux_mdio(priv->muxval);
+
+	return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int t208xqds_mdio_reset(struct mii_dev *bus)
+{
+	struct t208xqds_mdio *priv = bus->priv;
+
+	return priv->realbus->reset(priv->realbus);
+}
+
+static int t208xqds_mdio_init(char *realbusname, u8 muxval)
+{
+	struct t208xqds_mdio *pmdio;
+	struct mii_dev *bus = mdio_alloc();
+
+	if (!bus) {
+		printf("Failed to allocate t208xqds MDIO bus\n");
+		return -1;
+	}
+
+	pmdio = malloc(sizeof(*pmdio));
+	if (!pmdio) {
+		printf("Failed to allocate t208xqds private data\n");
+		free(bus);
+		return -1;
+	}
+
+	bus->read = t208xqds_mdio_read;
+	bus->write = t208xqds_mdio_write;
+	bus->reset = t208xqds_mdio_reset;
+	sprintf(bus->name, t208xqds_mdio_name_for_muxval(muxval));
+
+	pmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+	if (!pmdio->realbus) {
+		printf("No bus with name %s\n", realbusname);
+		free(bus);
+		free(pmdio);
+		return -1;
+	}
+
+	pmdio->muxval = muxval;
+	bus->priv = pmdio;
+	return mdio_register(bus);
+}
+
+void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
+				enum fm_port port, int offset)
+{
+	int phy;
+	char alias[20];
+	struct fixed_link f_link;
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
+				FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+
+	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+	if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
+		phy = fm_info_get_phy_address(port);
+		switch (port) {
+#if defined(CONFIG_T2080QDS)
+		case FM1_DTSEC1:
+		case FM1_DTSEC2:
+		case FM1_DTSEC9:
+		case FM1_DTSEC10:
+			if (mdio_mux[port] == EMI1_SLOT2) {
+				sprintf(alias, "phy_sgmii_s2_%x", phy);
+				fdt_set_phy_handle(fdt, compat, addr, alias);
+				fdt_status_okay_by_alias(fdt, "emi1_slot2");
+			} else if (mdio_mux[port] == EMI1_SLOT3) {
+				sprintf(alias, "phy_sgmii_s3_%x", phy);
+				fdt_set_phy_handle(fdt, compat, addr, alias);
+				fdt_status_okay_by_alias(fdt, "emi1_slot3");
+			}
+			break;
+		case FM1_DTSEC5:
+		case FM1_DTSEC6:
+			if (mdio_mux[port] == EMI1_SLOT1) {
+				sprintf(alias, "phy_sgmii_s1_%x", phy);
+				fdt_set_phy_handle(fdt, compat, addr, alias);
+				fdt_status_okay_by_alias(fdt, "emi1_slot1");
+			} else if (mdio_mux[port] == EMI1_SLOT2) {
+				sprintf(alias, "phy_sgmii_s2_%x", phy);
+				fdt_set_phy_handle(fdt, compat, addr, alias);
+				fdt_status_okay_by_alias(fdt, "emi1_slot2");
+			}
+			break;
+#elif defined(CONFIG_T2081QDS)
+		case FM1_DTSEC1:
+		case FM1_DTSEC2:
+		case FM1_DTSEC5:
+		case FM1_DTSEC6:
+		case FM1_DTSEC9:
+		case FM1_DTSEC10:
+			if (mdio_mux[port] == EMI1_SLOT2) {
+				sprintf(alias, "phy_sgmii_s2_%x", phy);
+				fdt_set_phy_handle(fdt, compat, addr, alias);
+				fdt_status_okay_by_alias(fdt, "emi1_slot2");
+			} else if (mdio_mux[port] == EMI1_SLOT3) {
+				sprintf(alias, "phy_sgmii_s3_%x", phy);
+				fdt_set_phy_handle(fdt, compat, addr, alias);
+				fdt_status_okay_by_alias(fdt, "emi1_slot3");
+			} else if (mdio_mux[port] == EMI1_SLOT5) {
+				sprintf(alias, "phy_sgmii_s5_%x", phy);
+				fdt_set_phy_handle(fdt, compat, addr, alias);
+				fdt_status_okay_by_alias(fdt, "emi1_slot5");
+			} else if (mdio_mux[port] == EMI1_SLOT6) {
+				sprintf(alias, "phy_sgmii_s6_%x", phy);
+				fdt_set_phy_handle(fdt, compat, addr, alias);
+				fdt_status_okay_by_alias(fdt, "emi1_slot6");
+			} else if (mdio_mux[port] == EMI1_SLOT7) {
+				sprintf(alias, "phy_sgmii_s7_%x", phy);
+				fdt_set_phy_handle(fdt, compat, addr, alias);
+				fdt_status_okay_by_alias(fdt, "emi1_slot7");
+			}
+			break;
+#endif
+		default:
+			break;
+		}
+
+	} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
+		switch (srds_s1) {
+		case 0x66: /* XFI interface */
+		case 0x6b:
+		case 0x6c:
+		case 0x6d:
+		case 0x71:
+			f_link.phy_id = port;
+			f_link.duplex = 1;
+			f_link.link_speed = 10000;
+			f_link.pause = 0;
+			f_link.asym_pause = 0;
+			/* no PHY for XFI */
+			fdt_delprop(fdt, offset, "phy-handle");
+			fdt_setprop(fdt, offset, "fixed-link", &f_link,
+				    sizeof(f_link));
+			break;
+		default:
+			break;
+		}
+	}
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+	return;
+}
+
+/*
+ * This function reads RCW to check if Serdes1{A:H} is configured
+ * to slot 1/2/3/4/5/6/7 and update the lane_to_slot[] array accordingly
+ */
+static void initialize_lane_to_slot(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
+				FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+
+	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+	switch (srds_s1) {
+#if defined(CONFIG_T2080QDS)
+	case 0x51:
+	case 0x5f:
+	case 0x65:
+	case 0x6b:
+	case 0x71:
+		lane_to_slot[5] = 2;
+		lane_to_slot[6] = 2;
+		lane_to_slot[7] = 2;
+		break;
+	case 0xa6:
+	case 0x8e:
+	case 0x8f:
+	case 0x82:
+	case 0x83:
+	case 0xd3:
+	case 0xd9:
+	case 0xcb:
+		lane_to_slot[6] = 2;
+		lane_to_slot[7] = 2;
+		break;
+	case 0xda:
+		lane_to_slot[4] = 3;
+		lane_to_slot[5] = 3;
+		lane_to_slot[6] = 3;
+		lane_to_slot[7] = 3;
+		break;
+#elif defined(CONFIG_T2081QDS)
+	case 0x6b:
+		lane_to_slot[4] = 1;
+		lane_to_slot[5] = 3;
+		lane_to_slot[6] = 3;
+		lane_to_slot[7] = 3;
+		break;
+	case 0xca:
+	case 0xcb:
+		lane_to_slot[1] = 7;
+		lane_to_slot[2] = 6;
+		lane_to_slot[3] = 5;
+		lane_to_slot[5] = 3;
+		lane_to_slot[6] = 3;
+		lane_to_slot[7] = 3;
+		break;
+	case 0xf2:
+		lane_to_slot[1] = 7;
+		lane_to_slot[2] = 7;
+		lane_to_slot[3] = 7;
+		lane_to_slot[5] = 4;
+		lane_to_slot[6] = 3;
+		lane_to_slot[7] = 7;
+		break;
+#endif
+	default:
+		break;
+	}
+}
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_FMAN_ENET)
+	int i, idx, lane, slot, interface;
+	struct memac_mdio_info dtsec_mdio_info;
+	struct memac_mdio_info tgec_mdio_info;
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
+	u32 srds_s1;
+
+	srds_s1 = in_be32(&gur->rcwsr[4]) &
+					FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+	initialize_lane_to_slot();
+
+	/* Initialize the mdio_mux array so we can recognize empty elements */
+	for (i = 0; i < NUM_FM_PORTS; i++)
+		mdio_mux[i] = EMI_NONE;
+
+	dtsec_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+
+	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+	/* Register the 1G MDIO bus */
+	fm_memac_mdio_init(bis, &dtsec_mdio_info);
+
+	tgec_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+	/* Register the 10G MDIO bus */
+	fm_memac_mdio_init(bis, &tgec_mdio_info);
+
+	/* Register the muxing front-ends to the MDIO buses */
+	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
+	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
+	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
+	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
+	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
+#if defined(CONFIG_T2080QDS)
+	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
+#endif
+	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
+#if defined(CONFIG_T2081QDS)
+	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
+	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
+#endif
+	t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
+
+	/* Set the two on-board RGMII PHY address */
+	fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
+	if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
+			FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII)
+		fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
+	else
+		fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR);
+
+	switch (srds_s1) {
+	case 0x1c:
+	case 0x95:
+	case 0xa2:
+	case 0x94:
+		/* T2080QDS: SGMII in Slot3;  T2081QDS: SGMII in Slot2 */
+		fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
+		/* T2080QDS: SGMII in Slot2;  T2081QDS: SGMII in Slot1 */
+		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
+		break;
+	case 0x51:
+	case 0x5f:
+	case 0x65:
+		/* T2080QDS: XAUI/HiGig in Slot3;  T2081QDS: in Slot2 */
+		fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
+		/* T2080QDS: SGMII in Slot2;  T2081QDS: in Slot3 */
+		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
+		break;
+	case 0x66:
+		/*
+		 * XFI does not need a PHY to work, but to avoid U-boot use
+		 * default PHY address which is zero to a MAC when it found
+		 * a MAC has no PHY address, we give a PHY address to XFI
+		 * MAC, and should not use a real XAUI PHY address, since
+		 * MDIO can access it successfully, and then MDIO thinks
+		 * the XAUI card is used for the XFI MAC, which will cause
+		 * error.
+		 */
+		fm_info_set_phy_address(FM1_10GEC1, 4);
+		fm_info_set_phy_address(FM1_10GEC2, 5);
+		fm_info_set_phy_address(FM1_10GEC3, 6);
+		fm_info_set_phy_address(FM1_10GEC4, 7);
+		break;
+	case 0x6b:
+		fm_info_set_phy_address(FM1_10GEC1, 4);
+		fm_info_set_phy_address(FM1_10GEC2, 5);
+		fm_info_set_phy_address(FM1_10GEC3, 6);
+		fm_info_set_phy_address(FM1_10GEC4, 7);
+		/* T2080QDS: SGMII in Slot2;  T2081QDS: in Slot3 */
+		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+		break;
+	case 0x6c:
+	case 0x6d:
+		fm_info_set_phy_address(FM1_10GEC1, 4);
+		fm_info_set_phy_address(FM1_10GEC2, 5);
+		/* T2080QDS: SGMII in Slot3;  T2081QDS: in Slot2 */
+		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
+		break;
+	case 0x71:
+		/* SGMII in Slot3 */
+		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
+		/* SGMII in Slot2 */
+		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+		break;
+	case 0xa6:
+	case 0x8e:
+	case 0x8f:
+	case 0x82:
+	case 0x83:
+		/* SGMII in Slot3 */
+		fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
+		/* SGMII in Slot2 */
+		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+		break;
+	case 0xa4:
+	case 0x96:
+	case 0x8a:
+		/* SGMII in Slot3 */
+		fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
+		break;
+#if defined(CONFIG_T2080QDS)
+	case 0xd9:
+	case 0xd3:
+	case 0xcb:
+		/* SGMII in Slot3 */
+		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
+		/* SGMII in Slot2 */
+		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+		break;
+#elif defined(CONFIG_T2081QDS)
+	case 0xca:
+	case 0xcb:
+		/* SGMII in Slot3 */
+		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+		/* SGMII in Slot5 */
+		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
+		/* SGMII in Slot6 */
+		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
+		/* SGMII in Slot7 */
+		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
+		break;
+#endif
+	case 0xf2:
+		/* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */
+		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
+		break;
+	default:
+		break;
+	}
+
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+		idx = i - FM1_DTSEC1;
+		interface = fm_info_get_enet_if(i);
+		switch (interface) {
+		case PHY_INTERFACE_MODE_SGMII:
+			lane = serdes_get_first_lane(FSL_SRDS_1,
+					SGMII_FM1_DTSEC1 + idx);
+			if (lane < 0)
+				break;
+			slot = lane_to_slot[lane];
+			debug("FM1 at DTSEC%u expects SGMII in slot %u\n",
+			      idx + 1, slot);
+			if (QIXIS_READ(present2) & (1 << (slot - 1)))
+				fm_disable_port(i);
+
+			switch (slot) {
+			case 1:
+				mdio_mux[i] = EMI1_SLOT1;
+				fm_info_set_mdio(i, mii_dev_for_muxval(
+						 mdio_mux[i]));
+				break;
+			case 2:
+				mdio_mux[i] = EMI1_SLOT2;
+				fm_info_set_mdio(i, mii_dev_for_muxval(
+						 mdio_mux[i]));
+				break;
+			case 3:
+				mdio_mux[i] = EMI1_SLOT3;
+				fm_info_set_mdio(i, mii_dev_for_muxval(
+						 mdio_mux[i]));
+				break;
+#if defined(CONFIG_T2081QDS)
+			case 5:
+				mdio_mux[i] = EMI1_SLOT5;
+				fm_info_set_mdio(i, mii_dev_for_muxval(
+						 mdio_mux[i]));
+				break;
+			case 6:
+				mdio_mux[i] = EMI1_SLOT6;
+				fm_info_set_mdio(i, mii_dev_for_muxval(
+						 mdio_mux[i]));
+				break;
+			case 7:
+				mdio_mux[i] = EMI1_SLOT7;
+				fm_info_set_mdio(i, mii_dev_for_muxval(
+						 mdio_mux[i]));
+				break;
+#endif
+			}
+			break;
+		case PHY_INTERFACE_MODE_RGMII:
+			if (i == FM1_DTSEC3)
+				mdio_mux[i] = EMI1_RGMII1;
+			else if (i == FM1_DTSEC4 || FM1_DTSEC10)
+				mdio_mux[i] = EMI1_RGMII2;
+			fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+			break;
+		default:
+			break;
+		}
+	}
+
+	for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
+		idx = i - FM1_10GEC1;
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_XGMII:
+			if (srds_s1 == 0x51) {
+				lane = serdes_get_first_lane(FSL_SRDS_1,
+						XAUI_FM1_MAC9 + idx);
+			} else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) {
+				lane = serdes_get_first_lane(FSL_SRDS_1,
+						HIGIG_FM1_MAC9 + idx);
+			} else {
+				if (i == FM1_10GEC1 || i == FM1_10GEC2)
+					lane = serdes_get_first_lane(FSL_SRDS_1,
+						XFI_FM1_MAC9 + idx);
+				else
+					lane = serdes_get_first_lane(FSL_SRDS_1,
+						XFI_FM1_MAC1 + idx);
+			}
+
+			if (lane < 0)
+				break;
+			mdio_mux[i] = EMI2;
+			fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+
+			if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) ||
+			    (srds_s1 == 0x6c) || (srds_s1 == 0x6d) ||
+			    (srds_s1 == 0x71)) {
+				/* As XFI is in cage intead of a slot, so
+				 * ensure doesn't disable the corresponding port
+				 */
+				break;
+			}
+
+			slot = lane_to_slot[lane];
+			if (QIXIS_READ(present2) & (1 << (slot - 1)))
+				fm_disable_port(i);
+			break;
+		default:
+			break;
+		}
+	}
+
+	cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+	return pci_eth_init(bis);
+}
diff --git a/board/freescale/t208xqds/law.c b/board/freescale/t208xqds/law.c
new file mode 100644
index 0000000..74e2a53
--- /dev/null
+++ b/board/freescale/t208xqds/law.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2008-2012 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef QIXIS_BASE_PHYS
+	SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	/* Limit DCSR to 32M to access NPC Trace Buffer */
+	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/t208xqds/pci.c b/board/freescale/t208xqds/pci.c
new file mode 100644
index 0000000..84a89da
--- /dev/null
+++ b/board/freescale/t208xqds/pci.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2007-2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+void pci_init_board(void)
+{
+	fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+	FT_FSL_PCI_SETUP;
+}
diff --git a/board/freescale/t208xqds/t2080_rcw.cfg b/board/freescale/t208xqds/t2080_rcw.cfg
new file mode 100644
index 0000000..c2ad0fd
--- /dev/null
+++ b/board/freescale/t208xqds/t2080_rcw.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#SerDes Protocol: 0x66_0x16
+#Core/DDR: 1533Mhz/2133MT/s
+12100017 15000000 00000000 00000000
+66160002 00008400 e8104000 c1000000
+00000000 00000000 00000000 000307fc
+00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xqds/t2081_rcw.cfg b/board/freescale/t208xqds/t2081_rcw.cfg
new file mode 100644
index 0000000..a2d5ecf
--- /dev/null
+++ b/board/freescale/t208xqds/t2081_rcw.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#Default SerDes Protocol: 0x6C
+#Core/DDR: 1533Mhz/2133MT/s
+12100017 15000000 00000000 00000000
+6c000002 00008000 e8104000 c1000000
+00000000 00000000 00000000 000307fc
+00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xqds/t208x_pbi.cfg b/board/freescale/t208xqds/t208x_pbi.cfg
new file mode 100644
index 0000000..e200d92
--- /dev/null
+++ b/board/freescale/t208xqds/t208x_pbi.cfg
@@ -0,0 +1,41 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+# Refer doc/README.pblimage for more details about how-to configure
+# and create PBL boot image
+#
+
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#512KB SRAM
+09010100 00000000
+09010104 fff80009
+09010f00 08000000
+#enable CPC1
+09010000 80000000
+#Configure LAW for CPC1
+09000d00 00000000
+09000d04 fff80000
+09000d08 81000012
+#Initialize eSPI controller, default configuration is slow for eSPI to
+#load data, this configuration comes from u-boot eSPI driver.
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Errata for slowing down the MDC clock to make it <= 2.5 MHZ
+094fc030 00008148
+094fd030 00008148
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Flush PBL data
+09138000 00000000
+091380c0 00000000
diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c
new file mode 100644
index 0000000..9cfc0bd
--- /dev/null
+++ b/board/freescale/t208xqds/t208xqds.c
@@ -0,0 +1,459 @@
+/*
+ * Copyright 2009-2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+
+#include "../common/qixis.h"
+#include "../common/vsc3316_3308.h"
+#include "t208xqds.h"
+#include "t208xqds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	char buf[64];
+	u8 sw;
+	struct cpu_type *cpu = gd->arch.cpu;
+	static const char *freq[4] = {
+		"100.00MHZ(from 8T49N222A)", "125.00MHz",
+		"156.25MHZ", "100.00MHz"
+	};
+
+	printf("Board: %sQDS, ", cpu->name);
+	sw = QIXIS_READ(arch);
+	printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
+	printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
+
+#ifdef CONFIG_SDCARD
+	puts("SD/MMC\n");
+#elif CONFIG_SPIFLASH
+	puts("SPI\n");
+#else
+	sw = QIXIS_READ(brdcfg[0]);
+	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+	if (sw < 0x8)
+		printf("vBank%d\n", sw);
+	else if (sw == 0x8)
+		puts("Promjet\n");
+	else if (sw == 0x9)
+		puts("NAND\n");
+	else
+		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+#endif
+
+	printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver),
+	       qixis_read_tag(buf), (int)qixis_read_minor());
+	/* the timestamp string contains "\n" at the end */
+	printf(" on %s", qixis_read_time(buf));
+
+	puts("SERDES Reference Clocks:\n");
+	sw = QIXIS_READ(brdcfg[2]);
+	printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6],
+	       freq[(sw >> 4) & 0x3]);
+	printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2],
+	       freq[sw & 0x3]);
+
+	return 0;
+}
+
+int select_i2c_ch_pca9547(u8 ch)
+{
+	int ret;
+
+	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+	if (ret) {
+		puts("PCA: failed to select proper channel\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+int brd_mux_lane_to_slot(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 srds_prtcl_s1;
+
+	srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
+				FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+	srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+#if defined(CONFIG_T2080QDS)
+	u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
+				FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+	srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+#endif
+
+	switch (srds_prtcl_s1) {
+	case 0:
+		/* SerDes1 is not enabled */
+		break;
+#if defined(CONFIG_T2080QDS)
+	case 0x1c:
+	case 0xa2:
+		/* SD1(A:D) => SLOT3 SGMII
+		 * SD1(G:H) => SLOT1 SGMII
+		 */
+		QIXIS_WRITE(brdcfg[12], 0x1a);
+		break;
+	case 0x94:
+	case 0x95:
+		/* SD1(A:B) => SLOT3 SGMII at 1.25bps
+		 * SD1(C:D) => SFP Module, SGMII at 3.125bps
+		 * SD1(E:H) => SLOT1 SGMII at 1.25bps
+		 */
+	case 0x96:
+		/* SD1(A:B) => SLOT3 SGMII at 1.25bps
+		 * SD1(C)   => SFP Module, SGMII at 3.125bps
+		 * SD1(D)   => SFP Module, SGMII at 1.25bps
+		 * SD1(E:H) => SLOT1 PCIe4 x4
+		 */
+		QIXIS_WRITE(brdcfg[12], 0x3a);
+		break;
+	case 0x51:
+		/* SD1(A:D) => SLOT3 XAUI
+		 * SD1(E)   => SLOT1 PCIe4
+		 * SD1(F:H) => SLOT2 SGMII
+		 */
+		QIXIS_WRITE(brdcfg[12], 0x15);
+		break;
+	case 0x66:
+	case 0x67:
+		/* SD1(A:D) => XFI cage
+		 * SD1(E:H) => SLOT1 PCIe4
+		 */
+		QIXIS_WRITE(brdcfg[12], 0xfe);
+		break;
+	case 0x6b:
+		/* SD1(A:D) => XFI cage
+		 * SD1(E)   => SLOT1 PCIe4
+		 * SD1(F:H) => SLOT2 SGMII
+		 */
+		QIXIS_WRITE(brdcfg[12], 0xf1);
+		break;
+	case 0x6c:
+	case 0x6d:
+		/* SD1(A:B) => XFI cage
+		 * SD1(C:D) => SLOT3 SGMII
+		 * SD1(E:H) => SLOT1 PCIe4
+		 */
+		QIXIS_WRITE(brdcfg[12], 0xda);
+		break;
+	case 0x6e:
+		/* SD1(A:B) => SFP Module, XFI
+		 * SD1(C:D) => SLOT3 SGMII
+		 * SD1(E:F) => SLOT1 PCIe4 x2
+		 * SD1(G:H) => SLOT2 SGMII
+		 */
+		QIXIS_WRITE(brdcfg[12], 0xd9);
+		break;
+	case 0xda:
+		/* SD1(A:H) => SLOT3 PCIe3 x8
+		 */
+		 QIXIS_WRITE(brdcfg[12], 0x0);
+		 break;
+	case 0xc8:
+		/* SD1(A)   => SLOT3 PCIe3 x1
+		 * SD1(B)   => SFP Module, SGMII at 1.25bps
+		 * SD1(C:D) => SFP Module, SGMII at 3.125bps
+		 * SD1(E:F) => SLOT1 PCIe4 x2
+		 * SD1(G:H) => SLOT2 SGMII
+		 */
+		 QIXIS_WRITE(brdcfg[12], 0x79);
+		 break;
+	case 0xab:
+		/* SD1(A:D) => SLOT3 PCIe3 x4
+		 * SD1(E:H) => SLOT1 PCIe4 x4
+		 */
+		 QIXIS_WRITE(brdcfg[12], 0x1a);
+		 break;
+#elif defined(CONFIG_T2081QDS)
+	case 0x51:
+		/* SD1(A:D) => SLOT2 XAUI
+		 * SD1(E)   => SLOT1 PCIe4 x1
+		 * SD1(F:H) => SLOT3 SGMII
+		 */
+		QIXIS_WRITE(brdcfg[12], 0x98);
+		QIXIS_WRITE(brdcfg[13], 0x70);
+		break;
+	case 0x6b:
+		/* SD1(A:D) => XFI SFP Module
+		 * SD1(E)   => SLOT1 PCIe4 x1
+		 * SD1(F:H) => SLOT3 SGMII
+		 */
+		QIXIS_WRITE(brdcfg[12], 0x80);
+		QIXIS_WRITE(brdcfg[13], 0x70);
+		break;
+	case 0x6c:
+		/* SD1(A:B) => XFI SFP Module
+		 * SD1(C:D) => SLOT2 SGMII
+		 * SD1(E:H) => SLOT1 PCIe4 x4
+		 */
+		QIXIS_WRITE(brdcfg[12], 0xe8);
+		QIXIS_WRITE(brdcfg[13], 0x0);
+		break;
+	case 0x6d:
+		/* SD1(A:B) => XFI SFP Module
+		 * SD1(C:D) => SLOT2 SGMII
+		 * SD1(E:H) => SLOT1 PCIe4 x4
+		 */
+		QIXIS_WRITE(brdcfg[12], 0xe8);
+		QIXIS_WRITE(brdcfg[13], 0x0);
+		break;
+	case 0xaa:
+	case 0xab:
+		/* SD1(A:D) => SLOT2 PCIe3 x4
+		 * SD1(F:H) => SLOT1 SGMI4 x4
+		 */
+		QIXIS_WRITE(brdcfg[12], 0xf8);
+		QIXIS_WRITE(brdcfg[13], 0x0);
+		break;
+	case 0xca:
+	case 0xcb:
+		/* SD1(A)   => SLOT2 PCIe3 x1
+		 * SD1(B)   => SLOT7 SGMII
+		 * SD1(C)   => SLOT6 SGMII
+		 * SD1(D)   => SLOT5 SGMII
+		 * SD1(E)   => SLOT1 PCIe4 x1
+		 * SD1(F:H) => SLOT3 SGMII
+		 */
+		QIXIS_WRITE(brdcfg[12], 0x80);
+		QIXIS_WRITE(brdcfg[13], 0x70);
+		break;
+	case 0xde:
+	case 0xdf:
+		/* SD1(A:D) => SLOT2 PCIe3 x4
+		 * SD1(E)   => SLOT1 PCIe4 x1
+		 * SD1(F)   => SLOT4 PCIe1 x1
+		 * SD1(G)   => SLOT3 PCIe2 x1
+		 * SD1(H)   => SLOT7 SGMII
+		 */
+		QIXIS_WRITE(brdcfg[12], 0x98);
+		QIXIS_WRITE(brdcfg[13], 0x25);
+		break;
+	case 0xf2:
+		/* SD1(A)   => SLOT2 PCIe3 x1
+		 * SD1(B:D) => SLOT7 SGMII
+		 * SD1(E)   => SLOT1 PCIe4 x1
+		 * SD1(F)   => SLOT4 PCIe1 x1
+		 * SD1(G)   => SLOT3 PCIe2 x1
+		 * SD1(H)   => SLOT7 SGMII
+		 */
+		QIXIS_WRITE(brdcfg[12], 0x81);
+		QIXIS_WRITE(brdcfg[13], 0xa5);
+		break;
+#endif
+	default:
+		printf("WARNING: unsupported for SerDes1 Protocol %d\n",
+		       srds_prtcl_s1);
+		return -1;
+	}
+
+#ifdef CONFIG_T2080QDS
+	switch (srds_prtcl_s2) {
+	case 0:
+		/* SerDes2 is not enabled */
+		break;
+	case 0x01:
+	case 0x02:
+		/* SD2(A:H) => SLOT4 PCIe1 */
+		QIXIS_WRITE(brdcfg[13], 0x10);
+		break;
+	case 0x15:
+	case 0x16:
+		/*
+		 * SD2(A:D) => SLOT4 PCIe1
+		 * SD2(E:F) => SLOT5 PCIe2
+		 * SD2(G:H) => SATA1,SATA2
+		 */
+		QIXIS_WRITE(brdcfg[13], 0xb0);
+		break;
+	case 0x18:
+		/*
+		 * SD2(A:D) => SLOT4 PCIe1
+		 * SD2(E:F) => SLOT5 Aurora
+		 * SD2(G:H) => SATA1,SATA2
+		 */
+		QIXIS_WRITE(brdcfg[13], 0x78);
+		break;
+	case 0x1f:
+		/*
+		 * SD2(A:D) => SLOT4 PCIe1
+		 * SD2(E:H) => SLOT5 PCIe2
+		 */
+		QIXIS_WRITE(brdcfg[13], 0xa0);
+		break;
+	case 0x29:
+	case 0x2d:
+	case 0x2e:
+		/*
+		 * SD2(A:D) => SLOT4 SRIO2
+		 * SD2(E:H) => SLOT5 SRIO1
+		 */
+		QIXIS_WRITE(brdcfg[13], 0xa0);
+		break;
+	case 0x36:
+		/*
+		 * SD2(A:D) => SLOT4 SRIO2
+		 * SD2(E:F) => Aurora
+		 * SD2(G:H) => SATA1,SATA2
+		 */
+		QIXIS_WRITE(brdcfg[13], 0x78);
+		break;
+	default:
+		printf("WARNING: unsupported for SerDes2 Protocol %d\n",
+		       srds_prtcl_s2);
+		return -1;
+	}
+#endif
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+	/*
+	 * Remap Boot flash + PROMJET region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* invalidate existing TLB entry for flash + promjet */
+	disable_tlb(flash_esel);
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+	set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	setup_portals();
+#endif
+
+	/* Disable remote I2C connection to qixis fpga */
+	QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
+
+	brd_mux_lane_to_slot();
+	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+
+	return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
+	/* use accurate clock measurement */
+	int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
+	int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
+	u32 val;
+
+	val =  freq * base;
+	if (val) {
+		debug("SYS Clock measurement is: %d\n", val);
+		return val;
+	} else {
+		printf("Warning: SYS clock measurement is invalid, ");
+		printf("using value from brdcfg1.\n");
+	}
+#endif
+
+	switch (sysclk_conf & 0x0F) {
+	case QIXIS_SYSCLK_83:
+		return 83333333;
+	case QIXIS_SYSCLK_100:
+		return 100000000;
+	case QIXIS_SYSCLK_125:
+		return 125000000;
+	case QIXIS_SYSCLK_133:
+		return 133333333;
+	case QIXIS_SYSCLK_150:
+		return 150000000;
+	case QIXIS_SYSCLK_160:
+		return 160000000;
+	case QIXIS_SYSCLK_166:
+		return 166666666;
+	}
+	return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
+	/* use accurate clock measurement */
+	int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
+	int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
+	u32 val;
+
+	val =  freq * base;
+	if (val) {
+		debug("DDR Clock measurement is: %d\n", val);
+		return val;
+	} else {
+		printf("Warning: DDR clock measurement is invalid, ");
+		printf("using value from brdcfg1.\n");
+	}
+#endif
+
+	switch ((ddrclk_conf & 0x30) >> 4) {
+	case QIXIS_DDRCLK_100:
+		return 100000000;
+	case QIXIS_DDRCLK_125:
+		return 125000000;
+	case QIXIS_DDRCLK_133:
+		return 133333333;
+	}
+	return 66666666;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+	pci_of_setup(blob, bd);
+#endif
+
+	fdt_fixup_liodn(blob);
+	fdt_fixup_dr_usb(blob, bd);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+	fdt_fixup_fman_ethernet(blob);
+	fdt_fixup_board_enet(blob);
+#endif
+}
diff --git a/board/freescale/t208xqds/t208xqds.h b/board/freescale/t208xqds/t208xqds.h
new file mode 100644
index 0000000..39fcef2
--- /dev/null
+++ b/board/freescale/t208xqds/t208xqds.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2011-2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CORENET_DS_H__
+#define __CORENET_DS_H__
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, bd_t *bd);
+
+#endif
diff --git a/board/freescale/t208xqds/t208xqds_qixis.h b/board/freescale/t208xqds/t208xqds_qixis.h
new file mode 100644
index 0000000..bdcdc12
--- /dev/null
+++ b/board/freescale/t208xqds/t208xqds_qixis.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __T208xQDS_QIXIS_H__
+#define __T208xQDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for T208xQDS */
+
+#define QIXIS_SRDS1CLK_122		0x5a
+#define QIXIS_SRDS1CLK_125		0x5e
+
+
+/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK             0xE0
+#define BRDCFG4_EMISEL_SHIFT            5
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66                 0x0
+#define QIXIS_SYSCLK_83                 0x1
+#define QIXIS_SYSCLK_100                0x2
+#define QIXIS_SYSCLK_125                0x3
+#define QIXIS_SYSCLK_133                0x4
+#define QIXIS_SYSCLK_150                0x5
+#define QIXIS_SYSCLK_160                0x6
+#define QIXIS_SYSCLK_166                0x7
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66                 0x0
+#define QIXIS_DDRCLK_100                0x1
+#define QIXIS_DDRCLK_125                0x2
+#define QIXIS_DDRCLK_133                0x3
+
+#define BRDCFG5_IRE                     0x20    /* i2c Remote i2c1 enable */
+
+#define BRDCFG9_SFP_TX_EN		0x10
+
+#define BRDCFG12_SD3EN_MASK             0x20
+#define BRDCFG12_SD3MX_MASK             0x08
+#define BRDCFG12_SD3MX_SLOT5            0x08
+#define BRDCFG12_SD3MX_SLOT6            0x00
+#define BRDCFG12_SD4EN_MASK             0x04
+#define BRDCFG12_SD4MX_MASK             0x03
+#define BRDCFG12_SD4MX_SLOT7            0x02
+#define BRDCFG12_SD4MX_SLOT8            0x01
+#define BRDCFG12_SD4MX_AURO_SATA        0x00
+#endif
diff --git a/board/freescale/t208xqds/tlb.c b/board/freescale/t208xqds/tlb.c
new file mode 100644
index 0000000..62cd110
--- /dev/null
+++ b/board/freescale/t208xqds/tlb.c
@@ -0,0 +1,146 @@
+/*
+ * Copyright 2008-2013 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+	/*
+	 * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
+	 * SRAM is at 0xfff00000, it covered the 0xfffff000.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_1M, 1),
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+	/*
+	 * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
+	 * space is at 0xfff00000, it covered the 0xfffff000.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
+		      CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_1M, 1),
+#else
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_16M, 1),
+
+	/* *I*G* - Flash, localbus */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCIe 1, 0x80000000 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_512M, 1),
+
+	/* *I*G* - PCIe 2, 0xa0000000 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCIe 3, 0xb0000000 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_256M, 1),
+
+
+	/* *I*G* - PCIe 4, 0xc0000000 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCI I/O */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 7, BOOKE_PAGESZ_256K, 1),
+
+	/* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 9, BOOKE_PAGESZ_16M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 10, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 11, BOOKE_PAGESZ_16M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 12, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 13, BOOKE_PAGESZ_32M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+	/*
+	 * *I*G - NAND
+	 * entry 14 and 15 has been used hard coded, they will be disabled
+	 * in cpu_init_f, so we use entry 16 for nand.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 16, BOOKE_PAGESZ_64K, 1),
+#endif
+#ifdef QIXIS_BASE_PHYS
+	SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 17, BOOKE_PAGESZ_4K, 1),
+#endif
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+	/*
+	 * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
+	 * fetching ucode and ENV from master
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
+		      CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+		      0, 18, BOOKE_PAGESZ_1M, 1),
+#endif
+
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/boards.cfg b/boards.cfg
index 706ec96..b169510 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -972,11 +972,16 @@ Active  powerpc     mpc85xx        -           freescale       p2041rdb
 Active  powerpc     mpc85xx        -           freescale       t1040qds            T1040QDS                             T1040QDS:PPC_T1040                                                                                                                Poonam Aggrwal <poonam.aggrwal at freescale.com>
 Active  powerpc     mpc85xx        -           freescale       t104xrdb            T1040RDB                             T1040RDB:PPC_T1040                                                                                                                Poonam Aggrwal  <poonam.aggrwal at freescale.com>
 Active  powerpc     mpc85xx        -           freescale       t104xrdb            T1042RDB_PI                          T1042RDB_PI:PPC_T1042                                                                                                             Poonam Aggrwal  <poonam.aggrwal at freescale.com>
-Active  powerpc     mpc85xx        -           freescale       t2080qds            T2080QDS                             T2080QDS:PPC_T2080                                                                                                                -
-Active  powerpc     mpc85xx        -           freescale       t2080qds            T2080QDS_NAND                        T2080QDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000                                                                      -
-Active  powerpc     mpc85xx        -           freescale       t2080qds            T2080QDS_SDCARD                      T2080QDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000                                                                    -
-Active  powerpc     mpc85xx        -           freescale       t2080qds            T2080QDS_SPIFLASH                    T2080QDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000                                                                  -
-Active  powerpc     mpc85xx        -           freescale       t2080qds            T2080QDS_SRIO_PCIE_BOOT              T2080QDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000                                                                  -
+Active  powerpc     mpc85xx        -           freescale       t208xqds            T2080QDS              T208xQDS:PPC_T2080
+Active  powerpc     mpc85xx        -           freescale       t208xqds            T2080QDS_SDCARD       T208xQDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000
+Active  powerpc     mpc85xx        -           freescale       t208xqds            T2080QDS_SPIFLASH     T208xQDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000
+Active  powerpc     mpc85xx        -           freescale       t208xqds            T2080QDS_NAND         T208xQDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000
+Active  powerpc     mpc85xx        -           freescale       t208xqds            T2080QDS_SRIO_PCIE_BOOT      T208xQDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000
+Active  powerpc     mpc85xx        -           freescale       t208xqds            T2081QDS              T208xQDS:PPC_T2081
+Active  powerpc     mpc85xx        -           freescale       t208xqds            T2081QDS_SDCARD       T208xQDS:PPC_T2081,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000
+Active  powerpc     mpc85xx        -           freescale       t208xqds            T2081QDS_SPIFLASH     T208xQDS:PPC_T2081,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000
+Active  powerpc     mpc85xx        -           freescale       t208xqds            T2081QDS_NAND         T208xQDS:PPC_T2081,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000
+Active  powerpc     mpc85xx        -           freescale       t208xqds            T2081QDS_SRIO_PCIE_BOOT      T208xQDS:PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000
 Active  powerpc     mpc85xx        -           freescale       t4qds               T4160QDS                             T4240QDS:PPC_T4160                                                                                                                -
 Active  powerpc     mpc85xx        -           freescale       t4qds               T4160QDS_SDCARD                      T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000                                                                    -
 Active  powerpc     mpc85xx        -           freescale       t4qds               T4160QDS_SPIFLASH                    T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000                                                                  -
diff --git a/include/configs/T2080QDS.h b/include/configs/T2080QDS.h
deleted file mode 100644
index 9bd0fe2..0000000
--- a/include/configs/T2080QDS.h
+++ /dev/null
@@ -1,804 +0,0 @@
-/*
- * Copyright 2011-2013 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-/*
- * T2080 QDS board configuration file
- */
-
-#ifndef __T2080QDS_H
-#define __T2080QDS_H
-
-#define CONFIG_T2080QDS
-#define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
-#define CONFIG_MMC
-#define CONFIG_SPI_FLASH
-#define CONFIG_USB_EHCI
-#define CONFIG_FSL_SATA_V2
-#define CONFIG_SYS_SRIO		/* Enable Serial RapidIO Support */
-#define CONFIG_SRIO1		/* SRIO port 1 */
-#define CONFIG_SRIO2		/* SRIO port 2 */
-
-/* High Level Configuration Options */
-#define CONFIG_PHYS_64BIT
-#define CONFIG_BOOKE
-#define CONFIG_E500		/* BOOKE e500 family */
-#define CONFIG_E500MC		/* BOOKE e500mc family */
-#define CONFIG_SYS_BOOK3E_HV	/* Category E.HV supported */
-#define CONFIG_MP		/* support multiple processors */
-#define CONFIG_ENABLE_36BIT_PHYS
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP 1
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-#endif
-
-#define CONFIG_SYS_FSL_CPC	/* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC	CONFIG_NUM_DDR_CONTROLLERS
-#define CONFIG_FSL_IFC		/* Enable IFC Support */
-#define CONFIG_FSL_LAW		/* Use common FSL init code */
-#define CONFIG_ENV_OVERWRITE
-
-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
-#define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
-#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t2080qds/t2080_pbi.cfg
-#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t2080qds/t2080_rcw.cfg
-#endif
-
-#define CONFIG_SRIO_PCIE_BOOT_MASTER
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-/* Set 1M boot space */
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
-		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#define CONFIG_SYS_NO_FLASH
-#endif
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xeff40000
-#endif
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
-#endif
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BTB		/* toggle branch predition */
-#define CONFIG_DDR_ECC
-#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
-#endif
-
-#ifdef CONFIG_SYS_NO_FLASH
-#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
-#define CONFIG_ENV_IS_NOWHERE
-#endif
-#else
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#endif
-
-#if defined(CONFIG_SPIFLASH)
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_SPI_BUS	0
-#define CONFIG_ENV_SPI_CS	0
-#define CONFIG_ENV_SPI_MAX_HZ	10000000
-#define CONFIG_ENV_SPI_MODE	0
-#define CONFIG_ENV_SIZE		0x2000	   /* 8KB */
-#define CONFIG_ENV_OFFSET	0x100000   /* 1MB */
-#define CONFIG_ENV_SECT_SIZE	0x10000
-#elif defined(CONFIG_SDCARD)
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV	0
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_OFFSET	(512 * 1658)
-#elif defined(CONFIG_NAND)
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET	(7 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-#define CONFIG_ENV_IS_IN_REMOTE
-#define CONFIG_ENV_ADDR		0xffe20000
-#define CONFIG_ENV_SIZE		0x2000
-#elif defined(CONFIG_ENV_IS_NOWHERE)
-#define CONFIG_ENV_SIZE		0x2000
-#else
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
-#endif
-
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-unsigned long get_board_ddr_clk(void);
-#endif
-
-#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk()
-#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
-
-/*
- * Config the L3 Cache as L3 SRAM
- */
-#define CONFIG_SYS_INIT_L3_ADDR	 CONFIG_RAMBOOT_TEXT_BASE
-
-#define CONFIG_SYS_DCSRBAR	0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS	0xf00000000ull
-
-/* EEPROM */
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM	0
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
-
-/*
- * DDR Setup
- */
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_DIMM_SLOTS_PER_CTLR	1
-#define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
-#define CONFIG_DDR_SPD
-#define CONFIG_SYS_FSL_DDR3
-#undef CONFIG_FSL_DDR_INTERACTIVE
-#define CONFIG_SYS_SPD_BUS_NUM	0
-#define CONFIG_SYS_SDRAM_SIZE	2048	/* for fixed parameter use */
-#define SPD_EEPROM_ADDRESS1	0x51
-#define SPD_EEPROM_ADDRESS2	0x52
-#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
-#define CTRL_INTLV_PREFERED	cacheline
-
-/*
- * IFC Definitions
- */
-#define CONFIG_SYS_FLASH_BASE		0xe0000000
-#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
-#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
-				+ 0x8000000) | \
-				CSPR_PORT_SIZE_16 | \
-				CSPR_MSEL_NOR | \
-				CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EXT	(0xf)
-#define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
-				CSPR_PORT_SIZE_16 | \
-				CSPR_MSEL_NOR | \
-				CSPR_V)
-#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
-/* NOR Flash Timing Params */
-#define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
-
-#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
-				FTIM0_NOR_TEADC(0x5) | \
-				FTIM0_NOR_TEAHC(0x5))
-#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
-				FTIM1_NOR_TRAD_NOR(0x1A) |\
-				FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
-				FTIM2_NOR_TCH(0x4) | \
-				FTIM2_NOR_TWPH(0x0E) | \
-				FTIM2_NOR_TWP(0x1c))
-#define CONFIG_SYS_NOR_FTIM3	0x0
-
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS \
-					+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
-
-#define CONFIG_FSL_QIXIS	/* use common QIXIS code */
-#define QIXIS_BASE			0xffdf0000
-#define QIXIS_LBMAP_SWITCH		6
-#define QIXIS_LBMAP_MASK		0x0f
-#define QIXIS_LBMAP_SHIFT		0
-#define QIXIS_LBMAP_DFLTBANK		0x00
-#define QIXIS_LBMAP_ALTBANK		0x04
-#define QIXIS_RST_CTL_RESET		0x83
-#define QIXIS_RST_FORCE_MEM		0x1
-#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
-#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
-#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
-#define QIXIS_BASE_PHYS		(0xf00000000ull | QIXIS_BASE)
-
-#define CONFIG_SYS_CSPR3_EXT	(0xf)
-#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
-				| CSPR_PORT_SIZE_8 \
-				| CSPR_MSEL_GPCM \
-				| CSPR_V)
-#define CONFIG_SYS_AMASK3	IFC_AMASK(4*1024)
-#define CONFIG_SYS_CSOR3	0x0
-/* QIXIS Timing parameters for IFC CS3 */
-#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
-					FTIM0_GPCM_TEADC(0x0e) | \
-					FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
-					FTIM1_GPCM_TRAD(0x3f))
-#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
-					FTIM2_GPCM_TCH(0x0) | \
-					FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS3_FTIM3		0x0
-
-/* NAND Flash on IFC */
-#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_NAND_BASE		0xff800000
-#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
-
-#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
-				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
-				| CSPR_MSEL_NAND	 /* MSEL = NAND */ \
-				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
-
-#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
-				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
-				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */	    \
-				| CSOR_NAND_RAL_3	/* RAL = 2Byes */   \
-				| CSOR_NAND_PGS_2K	/* Page Size = 2K */\
-				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */\
-				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
-
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
-					FTIM0_NAND_TWP(0x18)    | \
-					FTIM0_NAND_TWCHT(0x07)  | \
-					FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
-					FTIM1_NAND_TWBE(0x39)   | \
-					FTIM1_NAND_TRR(0x0e)    | \
-					FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f)  | \
-					FTIM2_NAND_TREH(0x0a)   | \
-					FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3		0x0
-
-#define CONFIG_SYS_NAND_DDR_LAW		11
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
-
-#if defined(CONFIG_NAND)
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
-#else
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
-#endif
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
-
-#if defined(CONFIG_RAMBOOT_PBL)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_MONITOR_BASE	 CONFIG_SYS_TEXT_BASE
-#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
-#define CONFIG_MISC_INIT_R
-#define CONFIG_HWCONFIG
-
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe0ec000
-/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
-			((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
-			CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
-						GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX		1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
-#define CONFIG_SYS_BAUDRATE_TABLE	\
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
-
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-/* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
-#define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
-#define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
-#define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
-#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
-#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
-#define CONFIG_SYS_FSL_I2C_SPEED   100000
-#define CONFIG_SYS_FSL_I2C2_SPEED  100000
-#define CONFIG_SYS_FSL_I2C3_SPEED  100000
-#define CONFIG_SYS_FSL_I2C4_SPEED  100000
-#define I2C_MUX_PCA_ADDR_PRI	0x77 /* I2C bus multiplexer,primary */
-#define I2C_MUX_PCA_ADDR_SEC1	0x75 /* I2C bus multiplexer,secondary 1 */
-#define I2C_MUX_PCA_ADDR_SEC2	0x76 /* I2C bus multiplexer,secondary 2 */
-#define I2C_MUX_CH_DEFAULT	0x8
-
-
-/*
- * RapidIO
- */
-#define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
-#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
-#define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000 /* 256M */
-#define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
-#define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
-#define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000 /* 256M */
-/*
- * for slave u-boot IMAGE instored in master memory space,
- * PHYS must be aligned based on the SIZE
- */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x80000 /* 512K */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
-/*
- * for slave UCODE and ENV instored in master memory space,
- * PHYS must be aligned based on the SIZE
- */
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000	/* 256K */
-
-/* slave core release by master*/
-#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
-#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
-
-/*
- * SRIO_PCIE_BOOT - SLAVE
- */
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
-		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
-#endif
-
-/*
- * eSPI - Enhanced SPI
- */
-#ifdef CONFIG_SPI_FLASH
-#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH_SST
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_SPANSION
-#define CONFIG_CMD_SF
-#define CONFIG_SF_DEFAULT_SPEED	 10000000
-#define CONFIG_SF_DEFAULT_MODE	  0
-#endif
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-#define CONFIG_PCI		/* Enable PCI/PCIE */
-#define CONFIG_PCIE1		/* PCIE controler 1 */
-#define CONFIG_PCIE2		/* PCIE controler 2 */
-#define CONFIG_PCIE3		/* PCIE controler 3 */
-#define CONFIG_PCIE4		/* PCIE controler 4 */
-#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
-#define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
-/* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
-#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
-
-/* controller 2, Slot 2, tgtid 2, Base address 201000 */
-#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
-#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
-
-/* controller 3, Slot 1, tgtid 1, Base address 202000 */
-#define CONFIG_SYS_PCIE3_MEM_VIRT	0xb0000000
-#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc30000000ull
-#define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
-#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
-#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
-
-/* controller 4, Base address 203000 */
-#define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
-#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE4_MEM_PHYS	0xc40000000ull
-#define CONFIG_SYS_PCIE4_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
-#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata LSZ ADD */
-#define CONFIG_NET_MULTI
-#define CONFIG_E1000
-#define CONFIG_PCI_PNP		/* do pci plug-and-play */
-#define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
-#define CONFIG_DOS_PARTITION
-#endif
-
-/* Qman/Bman */
-#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
-#define CONFIG_SYS_BMAN_NUM_PORTALS	18
-#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
-#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
-#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
-#define CONFIG_SYS_QMAN_NUM_PORTALS	18
-#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
-#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
-#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
-
-#define CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_DPAA_PME
-#define CONFIG_SYS_PMAN
-#define CONFIG_SYS_DPAA_DCE
-#define CONFIG_SYS_DPAA_RMAN		/* RMan */
-#define CONFIG_SYS_INTERLAKEN
-
-/* Default address of microcode for the Linux Fman driver */
-#if defined(CONFIG_SPIFLASH)
-/*
- * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
- * env, so we got 0x110000.
- */
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH
-#define CONFIG_SYS_QE_FMAN_FW_ADDR	0x110000
-#elif defined(CONFIG_SDCARD)
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 825KB (1650 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
- */
-#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
-#define CONFIG_SYS_QE_FMAN_FW_ADDR	(512 * 1680)
-#elif defined(CONFIG_NAND)
-#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#define CONFIG_SYS_QE_FMAN_FW_ADDR	(8 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-/*
- * Slave has no ucode locally, it can fetch this from remote. When implementing
- * in two corenet boards, slave's ucode could be stored in master's memory
- * space, the address can be mapped from slave TLB->slave LAW->
- * slave SRIO or PCIE outbound window->master inbound window->
- * master LAW->the ucode address in master's memory space.
- */
-#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
-#define CONFIG_SYS_QE_FMAN_FW_ADDR	0xFFE00000
-#else
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_QE_FMAN_FW_ADDR	0xEFF00000
-#endif
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
-#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
-#endif /* CONFIG_NOBQFMAN */
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
-#define CONFIG_PHYLIB_10G
-#define CONFIG_PHY_VITESSE
-#define CONFIG_PHY_REALTEK
-#define CONFIG_PHY_TERANETICS
-#define RGMII_PHY1_ADDR	0x1
-#define RGMII_PHY2_ADDR	0x2
-#define FM1_10GEC1_PHY_ADDR	  0x3
-#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
-#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
-#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
-#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
-#endif
-
-#ifdef CONFIG_FMAN_ENET
-#define CONFIG_MII		/* MII PHY management */
-#define CONFIG_ETHPRIME		"FM1 at DTSEC3"
-#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
-#endif
-
-/*
- * SATA
- */
-#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
-#define CONFIG_SYS_SATA_MAX_DEVICE	2
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
-#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
-#define CONFIG_SATA2
-#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
-#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
-#define CONFIG_LBA48
-#define CONFIG_CMD_SATA
-#define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
-#endif
-
-/*
- * USB
- */
-#ifdef CONFIG_USB_EHCI
-#define CONFIG_CMD_USB
-#define CONFIG_USB_STORAGE
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_CMD_EXT2
-#define CONFIG_HAS_FSL_DR_USB
-#endif
-
-/*
- * SDHC
- */
-#ifdef CONFIG_MMC
-#define CONFIG_CMD_MMC
-#define CONFIG_FSL_ESDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-#endif
-
-/*
- * Environment
- */
-#define CONFIG_LOADS_ECHO	/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_ERRATA
-#define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SETEXPR
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_BDI
-
-#ifdef CONFIG_PCI
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_NET
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
-#define CONFIG_AUTO_COMPLETE		/* add autocompletion support */
-#define CONFIG_SYS_LOAD_ADDR	0x2000000 /* default load address */
-#define CONFIG_SYS_PROMPT	"=> "	  /* Monitor Command Prompt */
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_SYS_CBSIZE	1024	  /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE	256	  /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
-
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ROOTPATH	 "/opt/nfsroot"
-#define CONFIG_BOOTFILE	 "uImage"
-#define CONFIG_UBOOTPATH "u-boot.bin"	/* U-Boot image on TFTP server */
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR		1000000
-#define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
-#define __USB_PHY_TYPE		utmi
-
-#define	CONFIG_EXTRA_ENV_SETTINGS				\
-	"hwconfig=fsl_ddr:"					\
-	"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","	\
-	"bank_intlv=auto;"					\
-	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
-	"netdev=eth0\0"						\
-	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
-	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
-	"tftpflash=tftpboot $loadaddr $uboot && "		\
-	"protect off $ubootaddr +$filesize && "			\
-	"erase $ubootaddr +$filesize && "			\
-	"cp.b $loadaddr $ubootaddr $filesize && "		\
-	"protect on $ubootaddr +$filesize && "			\
-	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
-	"consoledev=ttyS0\0"					\
-	"ramdiskaddr=2000000\0"					\
-	"ramdiskfile=t2080qds/ramdisk.uboot\0"			\
-	"fdtaddr=c00000\0"					\
-	"fdtfile=t2080qds/t2080qds.dtb\0"			\
-	"bdev=sda3\0"						\
-	"c=ffe\0"
-
-/*
- * For emulation this causes u-boot to jump to the start of the
- * proof point app code automatically
- */
-#define CONFIG_PROOF_POINTS				\
-	"setenv bootargs root=/dev/$bdev rw "		\
-	"console=$consoledev,$baudrate $othbootargs;"	\
-	"cpu 1 release 0x29000000 - - -;"		\
-	"cpu 2 release 0x29000000 - - -;"		\
-	"cpu 3 release 0x29000000 - - -;"		\
-	"cpu 4 release 0x29000000 - - -;"		\
-	"cpu 5 release 0x29000000 - - -;"		\
-	"cpu 6 release 0x29000000 - - -;"		\
-	"cpu 7 release 0x29000000 - - -;"		\
-	"go 0x29000000"
-
-#define CONFIG_HVBOOT				\
-	"setenv bootargs config-addr=0x60000000; "	\
-	"bootm 0x01000000 - 0x00f00000"
-
-#define CONFIG_ALU				\
-	"setenv bootargs root=/dev/$bdev rw "		\
-	"console=$consoledev,$baudrate $othbootargs;"	\
-	"cpu 1 release 0x01000000 - - -;"		\
-	"cpu 2 release 0x01000000 - - -;"		\
-	"cpu 3 release 0x01000000 - - -;"		\
-	"cpu 4 release 0x01000000 - - -;"		\
-	"cpu 5 release 0x01000000 - - -;"		\
-	"cpu 6 release 0x01000000 - - -;"		\
-	"cpu 7 release 0x01000000 - - -;"		\
-	"go 0x01000000"
-
-#define CONFIG_LINUX				\
-	"setenv bootargs root=/dev/ram rw "		\
-	"console=$consoledev,$baudrate $othbootargs;"	\
-	"setenv ramdiskaddr 0x02000000;"		\
-	"setenv fdtaddr 0x00c00000;"			\
-	"setenv loadaddr 0x1000000;"			\
-	"bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_HDBOOT					\
-	"setenv bootargs root=/dev/$bdev rw "		\
-	"console=$consoledev,$baudrate $othbootargs;"	\
-	"tftp $loadaddr $bootfile;"			\
-	"tftp $fdtaddr $fdtfile;"			\
-	"bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_NFSBOOTCOMMAND			\
-	"setenv bootargs root=/dev/nfs rw "	\
-	"nfsroot=$serverip:$rootpath "		\
-	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
-	"console=$consoledev,$baudrate $othbootargs;"	\
-	"tftp $loadaddr $bootfile;"		\
-	"tftp $fdtaddr $fdtfile;"		\
-	"bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND				\
-	"setenv bootargs root=/dev/ram rw "		\
-	"console=$consoledev,$baudrate $othbootargs;"	\
-	"tftp $ramdiskaddr $ramdiskfile;"		\
-	"tftp $loadaddr $bootfile;"			\
-	"tftp $fdtaddr $fdtfile;"			\
-	"bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND		CONFIG_LINUX
-
-#ifdef CONFIG_SECURE_BOOT
-#include <asm/fsl_secure_boot.h>
-#undef CONFIG_CMD_USB
-#endif
-
-#endif	/* __T2080QDS_H */
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
new file mode 100644
index 0000000..36afe9e
--- /dev/null
+++ b/include/configs/T208xQDS.h
@@ -0,0 +1,817 @@
+/*
+ * Copyright 2011-2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/*
+ * T2080/T2081 QDS board configuration file
+ */
+
+#ifndef __T208xQDS_H
+#define __T208xQDS_H
+
+#define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
+#define CONFIG_MMC
+#define CONFIG_SPI_FLASH
+#define CONFIG_USB_EHCI
+#if defined(CONFIG_PPC_T2080)
+#define CONFIG_T2080QDS
+#define CONFIG_FSL_SATA_V2
+#define CONFIG_SYS_SRIO		/* Enable Serial RapidIO Support */
+#define CONFIG_SRIO1		/* SRIO port 1 */
+#define CONFIG_SRIO2		/* SRIO port 2 */
+#elif defined(CONFIG_PPC_T2081)
+#define CONFIG_T2081QDS
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_PHYS_64BIT
+#define CONFIG_BOOKE
+#define CONFIG_E500		/* BOOKE e500 family */
+#define CONFIG_E500MC		/* BOOKE e500mc family */
+#define CONFIG_SYS_BOOK3E_HV	/* Category E.HV supported */
+#define CONFIG_MP		/* support multiple processors */
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP 1
+#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
+#endif
+
+#define CONFIG_SYS_FSL_CPC	/* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC	CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_FSL_IFC		/* Enable IFC Support */
+#define CONFIG_FSL_LAW		/* Use common FSL init code */
+#define CONFIG_ENV_OVERWRITE
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
+#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t208xqds/t208x_pbi.cfg
+#if defined(CONFIG_PPC_T2080)
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t208xqds/t2080_rcw.cfg
+#elif defined(CONFIG_PPC_T2081)
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t208xqds/t2081_rcw.cfg
+#endif
+#endif
+
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+/* Set 1M boot space */
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xeff40000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BTB		/* toggle branch predition */
+#define CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#endif
+
+#ifdef CONFIG_SYS_NO_FLASH
+#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+#else
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#endif
+
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS	0
+#define CONFIG_ENV_SPI_CS	0
+#define CONFIG_ENV_SPI_MAX_HZ	10000000
+#define CONFIG_ENV_SPI_MODE	0
+#define CONFIG_ENV_SIZE		0x2000	   /* 8KB */
+#define CONFIG_ENV_OFFSET	0x100000   /* 1MB */
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV	0
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_OFFSET	(512 * 1658)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET	(7 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+#define CONFIG_ENV_IS_IN_REMOTE
+#define CONFIG_ENV_ADDR		0xffe20000
+#define CONFIG_ENV_SIZE		0x2000
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE		0x2000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk()
+#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
+
+/*
+ * Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR	 CONFIG_RAMBOOT_TEXT_BASE
+
+#define CONFIG_SYS_DCSRBAR	0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS	0xf00000000ull
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_FSL_DDR3
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SYS_SPD_BUS_NUM	0
+#define CONFIG_SYS_SDRAM_SIZE	2048	/* for fixed parameter use */
+#define SPD_EEPROM_ADDRESS1	0x51
+#define SPD_EEPROM_ADDRESS2	0x52
+#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
+#define CTRL_INTLV_PREFERED	cacheline
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE		0xe0000000
+#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+				+ 0x8000000) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
+
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+				FTIM0_NOR_TEADC(0x5) | \
+				FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1A) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+				FTIM2_NOR_TCH(0x4) | \
+				FTIM2_NOR_TWPH(0x0E) | \
+				FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3	0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS \
+					+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+
+#define CONFIG_FSL_QIXIS	/* use common QIXIS code */
+#define QIXIS_BASE			0xffdf0000
+#define QIXIS_LBMAP_SWITCH		6
+#define QIXIS_LBMAP_MASK		0x0f
+#define QIXIS_LBMAP_SHIFT		0
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x04
+#define QIXIS_RST_CTL_RESET		0x83
+#define QIXIS_RST_FORCE_MEM		0x1
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define QIXIS_BASE_PHYS		(0xf00000000ull | QIXIS_BASE)
+
+#define CONFIG_SYS_CSPR3_EXT	(0xf)
+#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+#define CONFIG_SYS_AMASK3	IFC_AMASK(4*1024)
+#define CONFIG_SYS_CSOR3	0x0
+/* QIXIS Timing parameters for IFC CS3 */
+#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+					FTIM0_GPCM_TEADC(0x0e) | \
+					FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
+					FTIM1_GPCM_TRAD(0x3f))
+#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
+					FTIM2_GPCM_TCH(0x0) | \
+					FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS3_FTIM3		0x0
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	 /* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */	    \
+				| CSOR_NAND_RAL_3	/* RAL = 2Byes */   \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */\
+				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */\
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+					FTIM0_NAND_TWP(0x18)    | \
+					FTIM0_NAND_TWCHT(0x07)  | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)   | \
+					FTIM1_NAND_TRR(0x0e)    | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f)  | \
+					FTIM2_NAND_TREH(0x0a)   | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW		11
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_MONITOR_BASE	 CONFIG_SYS_TEXT_BASE
+#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe0ec000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+			((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+			CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+						GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
+#define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
+#define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
+#define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
+#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
+#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
+#define CONFIG_SYS_FSL_I2C_SPEED   100000
+#define CONFIG_SYS_FSL_I2C2_SPEED  100000
+#define CONFIG_SYS_FSL_I2C3_SPEED  100000
+#define CONFIG_SYS_FSL_I2C4_SPEED  100000
+#define I2C_MUX_PCA_ADDR_PRI	0x77 /* I2C bus multiplexer,primary */
+#define I2C_MUX_PCA_ADDR_SEC1	0x75 /* I2C bus multiplexer,secondary 1 */
+#define I2C_MUX_PCA_ADDR_SEC2	0x76 /* I2C bus multiplexer,secondary 2 */
+#define I2C_MUX_CH_DEFAULT	0x8
+
+
+/*
+ * RapidIO
+ */
+#define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
+#define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
+#define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000 /* 256M */
+/*
+ * for slave u-boot IMAGE instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x80000 /* 512K */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+/*
+ * for slave UCODE and ENV instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000	/* 256K */
+
+/* slave core release by master*/
+#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
+
+/*
+ * SRIO_PCIE_BOOT - SLAVE
+ */
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+#endif
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#ifdef CONFIG_SPI_FLASH
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_STMICRO
+#if defined(CONFIG_T2080QDS)
+#define CONFIG_SPI_FLASH_SPANSION
+#elif defined(CONFIG_T2081QDS)
+#define CONFIG_SPI_FLASH_EON
+#endif
+
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED	 10000000
+#define CONFIG_SF_DEFAULT_MODE	  0
+#endif
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CONFIG_PCI		/* Enable PCI/PCIE */
+#define CONFIG_PCIE1		/* PCIE controler 1 */
+#define CONFIG_PCIE2		/* PCIE controler 2 */
+#define CONFIG_PCIE3		/* PCIE controler 3 */
+#define CONFIG_PCIE4		/* PCIE controler 4 */
+#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xb0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc30000000ull
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 4, Base address 203000 */
+#define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
+#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_PHYS	0xc40000000ull
+#define CONFIG_SYS_PCIE4_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
+#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_FSL_PCIE_RESET	   /* need PCIe reset errata */
+#define CONFIG_NET_MULTI
+#define CONFIG_E1000
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS	18
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_QMAN_NUM_PORTALS	18
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+#define CONFIG_SYS_PMAN
+#define CONFIG_SYS_DPAA_DCE
+#define CONFIG_SYS_DPAA_RMAN		/* RMan */
+#define CONFIG_SYS_INTERLAKEN
+
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	0x110000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 825KB (1650 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	(512 * 1680)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	(8 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+/*
+ * Slave has no ucode locally, it can fetch this from remote. When implementing
+ * in two corenet boards, slave's ucode could be stored in master's memory
+ * space, the address can be mapped from slave TLB->slave LAW->
+ * slave SRIO or PCIE outbound window->master inbound window->
+ * master LAW->the ucode address in master's memory space.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	0xFFE00000
+#else
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	0xEFF00000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_REALTEK
+#define CONFIG_PHY_TERANETICS
+#define RGMII_PHY1_ADDR	0x1
+#define RGMII_PHY2_ADDR	0x2
+#define FM1_10GEC1_PHY_ADDR	  0x3
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_MII		/* MII PHY management */
+#define CONFIG_ETHPRIME		"FM1 at DTSEC3"
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * SATA
+ */
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
+ * USB
+ */
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_EXT2
+#define CONFIG_HAS_FSL_DR_USB
+#endif
+
+/*
+ * SDHC
+ */
+#ifdef CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_BDI
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE		/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT	"=> "	  /* Monitor Command Prompt */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE	1024	  /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256	  /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH	 "/opt/nfsroot"
+#define CONFIG_BOOTFILE	 "uImage"
+#define CONFIG_UBOOTPATH "u-boot.bin"	/* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
+#define __USB_PHY_TYPE		utmi
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hwconfig=fsl_ddr:"					\
+	"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","	\
+	"bank_intlv=auto;"					\
+	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+	"netdev=eth0\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
+	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
+	"tftpflash=tftpboot $loadaddr $uboot && "		\
+	"protect off $ubootaddr +$filesize && "			\
+	"erase $ubootaddr +$filesize && "			\
+	"cp.b $loadaddr $ubootaddr $filesize && "		\
+	"protect on $ubootaddr +$filesize && "			\
+	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
+	"consoledev=ttyS0\0"					\
+	"ramdiskaddr=2000000\0"					\
+	"ramdiskfile=t2080qds/ramdisk.uboot\0"			\
+	"fdtaddr=c00000\0"					\
+	"fdtfile=t2080qds/t2080qds.dtb\0"			\
+	"bdev=sda3\0"						\
+	"c=ffe\0"
+
+/*
+ * For emulation this causes u-boot to jump to the start of the
+ * proof point app code automatically
+ */
+#define CONFIG_PROOF_POINTS				\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"cpu 1 release 0x29000000 - - -;"		\
+	"cpu 2 release 0x29000000 - - -;"		\
+	"cpu 3 release 0x29000000 - - -;"		\
+	"cpu 4 release 0x29000000 - - -;"		\
+	"cpu 5 release 0x29000000 - - -;"		\
+	"cpu 6 release 0x29000000 - - -;"		\
+	"cpu 7 release 0x29000000 - - -;"		\
+	"go 0x29000000"
+
+#define CONFIG_HVBOOT				\
+	"setenv bootargs config-addr=0x60000000; "	\
+	"bootm 0x01000000 - 0x00f00000"
+
+#define CONFIG_ALU				\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"cpu 1 release 0x01000000 - - -;"		\
+	"cpu 2 release 0x01000000 - - -;"		\
+	"cpu 3 release 0x01000000 - - -;"		\
+	"cpu 4 release 0x01000000 - - -;"		\
+	"cpu 5 release 0x01000000 - - -;"		\
+	"cpu 6 release 0x01000000 - - -;"		\
+	"cpu 7 release 0x01000000 - - -;"		\
+	"go 0x01000000"
+
+#define CONFIG_LINUX				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"setenv ramdiskaddr 0x02000000;"		\
+	"setenv fdtaddr 0x00c00000;"			\
+	"setenv loadaddr 0x1000000;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_HDBOOT					\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND			\
+	"setenv bootargs root=/dev/nfs rw "	\
+	"nfsroot=$serverip:$rootpath "		\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $ramdiskaddr $ramdiskfile;"		\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_LINUX
+
+#ifdef CONFIG_SECURE_BOOT
+#include <asm/fsl_secure_boot.h>
+#undef CONFIG_CMD_USB
+#endif
+
+#endif	/* __T208xQDS_H */
-- 
1.8.0




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