[U-Boot] [PATCH v2 2/2] socfpga: Adding Denali NAND driver support

[Chin Liang See]

To add the Denali NAND driver support into SOCFPGA. But it would
not enabled by default as Altera Cyclone V dev kit doesn't have
a NAND device on it.

Signed-off-by: Chin Liang See <clsee at altera.com>
Cc: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
Cc: David Woodhouse <David.Woodhouse at intel.com>
Cc: Brian Norris <computersforpeace at gmail.com>
Cc: Scott Wood <scottwood at freescale.com>
---
Changes for v2
- Enable this driver support for SOCFPGA
---
 .../include/asm/arch-socfpga/socfpga_base_addrs.h  |    2 ++
 include/configs/socfpga_cyclone5.h                 |   16 ++++++++++++++++
 2 files changed, 18 insertions(+)

diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
index 5f73824..dd3988b 100644
--- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
+++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
@@ -8,6 +8,8 @@
 #define _SOCFPGA_BASE_ADDRS_H_
 
 #define SOCFPGA_L3REGS_ADDRESS 0xff800000
+#define SOCFPGA_NAND_DATA_ADDRESS 0xff900000
+#define SOCFPGA_NAND_REGS_ADDRESS 0xffb80000
 #define SOCFPGA_UART0_ADDRESS 0xffc02000
 #define SOCFPGA_UART1_ADDRESS 0xffc03000
 #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
index 1b78ccb..7f26c14 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -216,6 +216,22 @@
 /* Clocks source frequency to watchdog timer */
 #define CONFIG_DW_WDT_CLOCK_KHZ		25000
 
+/* NAND */
+#undef CONFIG_NAND_DENALI
+#ifdef CONFIG_NAND_DENALI
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_REGS_BASE	SOCFPGA_NAND_REGS_ADDRESS
+#define CONFIG_SYS_NAND_DATA_BASE	SOCFPGA_NAND_DATA_ADDRESS
+#define CONFIG_SYS_NAND_BASE		CONFIG_SYS_NAND_REGS_BASE
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+/* How many bytes need to be skipped at the start of spare area */
+#define CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES	(2)
+/* The ECC size which either 512 or 1024 */
+#define CONFIG_NAND_DENALI_ECC_SIZE			(512)
+#endif /* CONFIG_NAND_DENALI */
+
 /*
  * SPL "Second Program Loader" aka Initial Software
  */
-- 
1.7.9.5