[U-Boot] [PATCH v3 2/2] socfpga: Adding DesignWare watchdog support
Chin Liang See
clsee at altera.com
Fri Feb 21 21:57:44 CET 2014
To enable the DesignWare watchdog support at SOCFPGA Cyclone V
dev kit.
Signed-off-by: Chin Liang See <clsee at altera.com>
Cc: Anatolij Gustschin <agust at denx.de>
Cc: Albert Aribaud <albert.u.boot at aribaud.net>
Cc: Heiko Schocher <hs at denx.de>
Cc: Tom Rini <trini at ti.com>
---
Changes for v3
- Split to 2 series patch
Changes for v2
- Enable this driver at socfpga_cyclone5 board
---
.../include/asm/arch-socfpga/socfpga_base_addrs.h | 1 +
include/configs/socfpga_cyclone5.h | 13 +++++++++++++
2 files changed, 14 insertions(+)
diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
index 20f12e0..5f73824 100644
--- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
+++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
@@ -11,6 +11,7 @@
#define SOCFPGA_UART0_ADDRESS 0xffc02000
#define SOCFPGA_UART1_ADDRESS 0xffc03000
#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
+#define SOCFPGA_L4WD0_ADDRESS 0xffd02000
#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000
diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
index fc921ee..1b78ccb 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -207,6 +207,16 @@
#define CONFIG_ENV_IS_NOWHERE
/*
+ * L4 Watchdog
+ */
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 2000
+#define CONFIG_DESIGNWARE_WATCHDOG
+#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
+/* Clocks source frequency to watchdog timer */
+#define CONFIG_DW_WDT_CLOCK_KHZ 25000
+
+/*
* SPL "Second Program Loader" aka Initial Software
*/
@@ -238,4 +248,7 @@
/* Support for lib/libgeneric.o in SPL binary */
#define CONFIG_SPL_LIBGENERIC_SUPPORT
+/* Support for watchdog */
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+
#endif /* __CONFIG_H */
--
1.7.9.5
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