[U-Boot] [PATCH 0/6][v2] powerpc: Add support 2 stage boot loader for corenet platform
Prabhakar Kushwaha
prabhakar at freescale.com
Fri Feb 28 09:49:32 CET 2014
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
---
Add support of 2 stage NAND boot loader in cornet platforms using SPL framework.
In current secenrio size of u-boot can become >=512KB. So This patch set will be
helpful for those SoC which has less internal SRAM(512KB).
here, PBL initialise the internal SRAM and copy SPL(192K) in SRAM.
SPL further initialise DDR using SPD and environment variables and copy
u-boot(768 KB) from flash to DDR.
Finally SPL transer control to u-boot for futher booting.
SPL has following features:
- Executes within 256K
- No relocation required
Run time view of SPL framework :-
-----------------------------------------------
Area | Address |
-----------------------------------------------
GD, BD | 0xFFFC0000 |
-----------------------------------------------
ENV | 0xFFFC1000 |
-----------------------------------------------
HEAP | 0xFFFC2800 |
-----------------------------------------------
STACK | 0xFFFD0000 |
-----------------------------------------------
U-boot SPL | 0xfffD0000 - 0xfffffffc (192K) |
-----------------------------------------------
NAND Flash memory Map on B4860 and B4420QDS
------------------------------------------
Start End Definition Size
0x000000 0x0FFFFF u-boot 1MB
0x140000 0x15FFFF u-boot env 128KB
0x160000 0x17FFFF FMAN Ucode 128KB
---
This patch set contains:-
[PATCH 1/6] powerpc/mpc85xx: Avoid hardcoding in SPL linker script
[PATCH 2/6] powerpc:Add support of SPL non-relocation
[PATCH 3/6] powerpc/mpc8xxx:Allow Parsing of LAW table in both SPL & non SPL
[PATCH 4/6] driver/ifc: define nand_spl_load_image() for SPL
[PATCH 5/6] Makefile: Add support of RAMBOOT_SPLPBL
[PATCH 6/6] B4860QDS: Add support of 2 stage NAND boot loader
--
1.7.9.5
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