[U-Boot] [PATCH] i.MX6: Ensure AHB clock is 132MHz in low freq boot mode

Hui.Liu at freescale.com Hui.Liu at freescale.com
Tue Jan 7 11:37:50 CET 2014


> -----Original Message-----
> From: Anson Huang [mailto:b20788 at freescale.com]
> Sent: Tuesday, January 07, 2014 5:32 AM
> To: sbabic at denx.de; eric.nelson at boundarydevices.com;
> troy.kisky at boundarydevices.com; Estevam Fabio-R49496; Liu Hui-R64343
> Cc: u-boot at lists.denx.de
> Subject: [PATCH] i.MX6: Ensure AHB clock is 132MHz in low freq boot mode
> 
> For low freq boot mode(ARM boot up with 396MHz), ROM will not set AHB
> clock to 132MHz, and the reset value of AHB divider is incorrect which
> will lead to wrong AHB rate, need to correct it. To enable low freq boot
> mode, need to set BOOT_CFG2[2] to high, tested on i.MX6Q/DL SabreSD board
> and i.MX6SL EVK board.
> 
> Signed-off-by: Anson Huang <b20788 at freescale.com>

Looks good to me.

Acked-by: Jason Liu <r64343 at freescale.com>

> ---
>  arch/arm/cpu/armv7/mx6/soc.c |   20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
> index a390296..edf3139 100644
> --- a/arch/arm/cpu/armv7/mx6/soc.c
> +++ b/arch/arm/cpu/armv7/mx6/soc.c
> @@ -131,10 +131,30 @@ static void imx_set_wdog_powerdown(bool enable)
>  	writew(enable, &wdog2->wmcr);
>  }
> 
> +static void set_ahb_rate(u32 val)
> +{
> +	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> +	u32 reg, div;
> +
> +	div = get_periph_clk() / val - 1;
> +	reg = readl(&mxc_ccm->cbcdr);
> +
> +	writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
> +		(div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr); }
> +
>  int arch_cpu_init(void)
>  {
>  	init_aips();
> 
> +	/*
> +	 * When low freq boot is enabled, ROM will not set AHB
> +	 * freq, so we need to ensure AHB freq is 132MHz in such
> +	 * scenario.
> +	 */
> +	if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
> +		set_ahb_rate(132000000);
> +
>  	set_vddsoc(1200);	/* Set VDDSOC to 1.2V */
> 
>  	imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register
> */
> --
> 1.7.9.5
> 



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