[U-Boot] [PATCH v4 12/29] zynq: Add zynq zed board support
Jagannadha Sutradharudu Teki
jagannadha.sutradharudu-teki at xilinx.com
Wed Jan 8 11:23:19 CET 2014
Zed is a complete development board based on the
Xilinx Zynq-7000 All Programmable SoC.
APSOC:
- XC7Z020-CLG484-1
Memory:
- 512 MB DDR3
- 256 Mb Quad-SPI Flash(
- Full size SD/MMC card cage
Connectivity:
- 10/100/1000 Ethernet
- USB OTG (Device/Host/OTG)
- USB-UART
Expansion:
- FMC (Low Pin Count)
- Pmod. headers (2x6)
Video/Display:
- HDMI output (1080p60 + audio)
- VGA connector
- 128 x 32 OLED
- User LEDs (9)
User inputs:
- Slide switches (8)
- Push button switches (7)
Audio:
- 24-bit stereo audio CODEC
- Stereo line in/out
- Headphone
- Microphone input
Analog:
- Xilinx XADC header
- Supports 4 analog inputs
- 2 Differential / 4 Single-ended
Debug:
- On-board USB JTAG programming port
- ARM Debug Access Port (DAP)
For more info - http://zedboard.org/product/zedboard
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna at xilinx.com>
---
boards.cfg | 1 +
include/configs/zynq_zed.h | 24 ++++++++++++++++++++++++
2 files changed, 25 insertions(+)
create mode 100644 include/configs/zynq_zed.h
diff --git a/boards.cfg b/boards.cfg
index 5ef2045..720aad6 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -355,6 +355,7 @@ Active arm armv7 u8500 st-ericsson snowball
Active arm armv7 u8500 st-ericsson u8500 u8500_href - -
Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang <b18965 at freescale.com>
Active arm armv7 zynq xilinx zynq zynq_zc70x - Michal Simek <monstr at monstr.eu>:Jagannadha Sutradharudu Teki <jaganna at xilinx.com>
+Active arm armv7 zynq xilinx zynq zynq_zed - Michal Simek <monstr at monstr.eu>:Jagannadha Sutradharudu Teki <jaganna at xilinx.com>
Active arm armv7:arm720t tegra114 nvidia dalmore dalmore - Tom Warren <twarren at nvidia.com>
Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Thierry Reding <thierry.reding at avionic-design.de>
Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Thierry Reding <thierry.reding at avionic-design.de>
diff --git a/include/configs/zynq_zed.h b/include/configs/zynq_zed.h
new file mode 100644
index 0000000..278db1e
--- /dev/null
+++ b/include/configs/zynq_zed.h
@@ -0,0 +1,24 @@
+/*
+ * (C) Copyright 2013 Xilinx, Inc.
+ *
+ * Configuration for Zynq Evaluation and Development Board - ZedBoard
+ * See zynq_common.h for Zynq common configs
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQ_ZED_H
+#define __CONFIG_ZYNQ_ZED_H
+
+#define CONFIG_ZYNQ_SERIAL_UART1
+#define CONFIG_ZYNQ_GEM0
+#define CONFIG_ZYNQ_GEM_PHY_ADDR0 0
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ZYNQ_SDHCI0
+#define CONFIG_ZYNQ_BOOT_FREEBSD
+
+#include <configs/zynq-common.h>
+
+#endif /* __CONFIG_ZYNQ_ZED_H */
--
1.8.3
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