[U-Boot] [PATCH] ARM: tegra20: Add a missing entry in the pullid enum

[Stephen Warren]

On 01/15/2014 07:55 AM, Alban Bedel wrote:
> It seems two entries were merged in one when this file has been
> created. The GPSLXAU entries is obviously a mix of GPU and SLXA which
> are next to each other according to the datasheet. Moreover it can be
> noticed because the APB_MISC_PP_PULLUPDOWN_REG_B_0 register only have
> 15 entries instead of 16.
> 
> Also fix the pin group descriptions that were using these buggy
> entries. In particular SLXA that needed to used CRTP to actually
> write the SLXA register.

This does appear to match the kernel's pinctrl driver, so,
Acked-by: Stephen Warren <swarren at nvidia.com>

I wonder how many more similar issues there are. Did you check the whole
file for this kind of issue, or just debug a problem with one particular
pin/group?