[U-Boot] [PATCH 2/2] imx6: make sure MMDC_CHx_MASK is clear to avoid warm reset failure

[Anson Huang]

Boot ROM may mask MMDC_CHx_MASK in CCM_CCDR(such as i.MX6SL TO1.2),
it will cause warm reset fail, need to clear this MMDC_CHx_MASK field
to make sure all the i.MX6 series SOCs reset function work. Otherwise,
uboot "reset" command will fail, tested on i.MX6SL EVK board with TO1.2.

Signed-off-by: Anson Huang <b20788 at freescale.com>
---
 arch/arm/cpu/armv7/mx6/soc.c |   11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 33a2939..2b162c2 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -189,10 +189,21 @@ static void set_ahb_rate(u32 val)
 		(div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
 }
 
+static void clear_mmdc_ch_mask()
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* Clear MMDC channel mask */
+	writel(0, &mxc_ccm->ccdr);
+}
+
 int arch_cpu_init(void)
 {
 	init_aips();
 
+	/* Need to clear MMDC_CHx_MASK to make warm reset work. */
+	clear_mmdc_ch_mask();
+
 	/*
 	 * When low freq boot is enabled, ROM will not set AHB
 	 * freq, so we need to ensure AHB freq is 132MHz in such
-- 
1.7.9.5