[U-Boot] [PATCH V3 02/14] ARM: tegra: misc cleanups triggered by Tegra124 review

[Stephen Warren]

From: Stephen Warren <swarren at nvidia.com>

Use a named constant for the PLL lock bit in enable_cpu_clocks().

Construct the complete value of pmc_pwrgate_toggle, rather than doing a
read-modify-write; the register is simple enough and doesn't need to
maintain state between operations.

Signed-off-by: Stephen Warren <swarren at nvidia.com>
Tested-by: Thierry Reding <treding at nvidia.com>
---
v3: Fixed #define indent
v2: New patch, split out from the later Tegra124 changes.
---
 arch/arm/cpu/arm720t/tegra114/cpu.c       | 6 ++----
 arch/arm/include/asm/arch-tegra/clk_rst.h | 3 +++
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/arm720t/tegra114/cpu.c b/arch/arm/cpu/arm720t/tegra114/cpu.c
index 385e1a1c86e0..a5de100140ab 100644
--- a/arch/arm/cpu/arm720t/tegra114/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra114/cpu.c
@@ -68,7 +68,7 @@ static void enable_cpu_clocks(void)
 	/* Wait for PLL-X to lock */
 	do {
 		reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
-	} while ((reg & (1 << 27)) == 0);
+	} while ((reg & PLL_LOCK_MASK) == 0);
 
 	/* Wait until all clocks are stable */
 	udelay(PLL_STABILIZATION_DELAY);
@@ -221,9 +221,7 @@ static void power_partition(u32 status, u32 partid)
 	if (!is_partition_powered(status)) {
 		/* No, toggle the partition power state (OFF -> ON) */
 		debug("power_partition, toggling state\n");
-		clrbits_le32(&pmc->pmc_pwrgate_toggle, 0x1F);
-		setbits_le32(&pmc->pmc_pwrgate_toggle, partid);
-		setbits_le32(&pmc->pmc_pwrgate_toggle, START_CP);
+		writel(START_CP | partid, &pmc->pmc_pwrgate_toggle);
 
 		/* Wait for the power to come up */
 		while (!is_partition_powered(status))
diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h
index 021cfcc3c602..cc608258b4e8 100644
--- a/arch/arm/include/asm/arch-tegra/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra/clk_rst.h
@@ -160,6 +160,9 @@ struct clk_rst_ctlr {
 
 #define PLL_BASE_OVRRIDE_MASK	(1U << 28)
 
+#define PLL_LOCK_SHIFT		27
+#define PLL_LOCK_MASK		(1U << PLL_LOCK_SHIFT)
+
 #define PLL_DIVP_SHIFT		20
 #define PLL_DIVP_MASK		(7U << PLL_DIVP_SHIFT)
 
-- 
1.8.1.5