[U-Boot] [PATCH v3] mx6: Enable L2 cache support

[Fabio Estevam]

Hi Dirk,

On Tue, Jan 28, 2014 at 2:53 PM, Dirk Behme <dirk.behme at gmail.com> wrote:

> Just for better understanding: Do you want to keep this intentionally
> simple? Or is there any special reason why you don't set additional
> (performance) registers here? E.g. the L2 PREFETCH and POWER registers, and
> the tag and data latency settings? Like done in the kernel.

The idea was to keep it simple initially and then we can extend L2
support as needed.

Regards,

Fabio Estevam