[U-Boot] [PATCH v2 3/6] PPC 85xx: Add qemu-ppce500 machine

[York Sun]

On 01/31/2014 03:16 AM, Alexander Graf wrote:
> For KVM we have a special PV machine type called "ppce500". This machine
> is inspired by the MPC8544DS board, but implements a lot less features
> than that one.
> 
> It also provides more PCI slots and is supposed to be enumerated by
> device tree only.
> 
> This patch adds support for the current generation ppce500 machine as
> it is implemented today.
> 
> Signed-off-by: Alexander Graf <agraf at suse.de>
> 
> ---
> 
> v1 -> v2:
> 
>   - Write device tree offset directly into global variable
>   - use r4 rather than r2 for that
>   - access fdt directly from in-memory copy
>   - remove unneeded header includes
>   - clean up pci enumeration
>   - coding style fixes
>   - populate and only use fdt_addr_r
>   - remove unused exported functions
>   - remove unused TLB0 entries
>   - make TLB1 I/O maps non-executable
>   - remove unused defines in board header
>   - make -kernel boot variables more clear
>   - remove TLB0 invalidation
>   - use tlb1.14 for temporary as=1 map
>   - use CONFIG_SYS_MPC85XX_NO_RESETVEC
>   - store fdt pointer in gd through cpu_init_early_f()
>   - replace fixup_tlb1() with dynamic TLB creation hook
> ---

<snip>

> diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
> index 8748ecd..c899d9e 100644
> --- a/arch/powerpc/cpu/mpc85xx/tlb.c
> +++ b/arch/powerpc/cpu/mpc85xx/tlb.c
> @@ -36,6 +36,10 @@ void init_tlbs(void)
>  			  tlb_table[i].mas7);
>  	}
>  
> +#ifdef CONFIG_USE_DYNAMIC_TLBS
> +	init_tlbs_dynamic();
> +#endif
> +

You are adding a new CONFIG to common files. Please document it.

>  	return ;
>  }
>  

<snip>

> diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h
> new file mode 100644
> index 0000000..1ebaf51
> --- /dev/null
> +++ b/include/configs/qemu-ppce500.h
> @@ -0,0 +1,209 @@
> +/*
> + * Copyright 2011-2014 Freescale Semiconductor, Inc.
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +
> +/*
> + * Corenet DS style board configuration file
> + */
> +#ifndef __QEMU_PPCE500_H
> +#define __QEMU_PPCE500_H
> +
> +#define CONFIG_CMD_REGINFO
> +
> +/* High Level Configuration Options */
> +#define CONFIG_BOOKE
> +#define CONFIG_E500			/* BOOKE e500 family */
> +#define CONFIG_MPC85xx			/* MPC85xx/PQ3 platform */
> +#define CONFIG_QEMU_E500
> +
> +#undef CONFIG_SYS_TEXT_BASE
> +#define CONFIG_SYS_TEXT_BASE	0xf01000 /* 15 MB */
> +
> +#define CONFIG_SYS_MPC85XX_NO_RESETVEC
> +
> +#define CONFIG_SYS_RAMBOOT
> +
> +#define CONFIG_PCI			/* Enable PCI/PCIE */
> +#define CONFIG_PCI1		1	/* PCI controller 1 */
> +#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
> +#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
> +
> +#define CONFIG_ENV_OVERWRITE
> +
> +#define CONFIG_ENABLE_36BIT_PHYS
> +
> +#define CONFIG_ADDR_MAP
> +#define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
> +
> +#define CONFIG_USE_DYNAMIC_TLBS
> +
> +#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
> +#define CONFIG_SYS_MEMTEST_END		0x00400000
> +#define CONFIG_SYS_ALT_MEMTEST
> +#define CONFIG_PANIC_HANG	/* do not reset board on panic */
> +
> +#define CONFIG_SYS_CCSRBAR		0xe0000000
> +#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
> +
> +/*
> + * DDR Setup
> + */
> +#define CONFIG_VERY_BIG_RAM
> +#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
> +#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
> +
> +#define CONFIG_CHIP_SELECTS_PER_CTRL	0

I don't know if the qemu has PCI, DDR, etc. Setting the above line to 0 will
actually disable DDR controllers. Is that what you want?

> +
> +/* Get RAM size from device tree */
> +#define CONFIG_DDR_SPD

You enabled SPD but I don't see the I2C address. Did you miss something, or you
don't really use SPD?

York