[U-Boot] [PATCH] wandboard: add Future Eletronics 7" WVGA LCD extension board

[Fabio Estevam]

On Thu, May 1, 2014 at 5:16 PM, Otavio Salvador <otavio at ossystems.com.br> wrote:
> This adds support for the 7" WVGA produced by Future Eletronics and
> make it dynamically detect if it is connected or not based on the
> touchscreen controller.

What kind of display is this? Parallel display or LVDS?

> -int board_video_skip(void)
> -{
> -       int ret;
> +static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = {
> +       MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
> +       MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* HSync */
> +       MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* VSync */
> +       MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04
> +               | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm), /* Contrast */
> +       MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* DISP0_DRDY */
> +
> +       MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
> +       MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
> +       MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
> +       MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
> +       MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
> +       MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
> +       MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
> +       MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
> +       MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
> +       MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
> +       MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
> +       MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
> +       MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
> +       MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
> +       MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
> +       MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
> +       MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
> +       MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,

It seems like this is a parallel display...

>  static void setup_display(void)
>  {
>         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> +       struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
>         int reg;
>
>         enable_ipu_clock();
>         imx_setup_hdmi();
>
> +       /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
> +       reg = __raw_readl(&mxc_ccm->CCGR3);
> +       reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
> +       writel(reg, &mxc_ccm->CCGR3);

,but here you turn on the LDB clocks, why?

> +
> +       /* set LDB0, LDB1 clk select to 011/011 */
> +       reg = readl(&mxc_ccm->cs2cdr);
> +       reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
> +                | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
> +       reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
> +             | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
> +       writel(reg, &mxc_ccm->cs2cdr);
> +
> +       reg = readl(&mxc_ccm->cscmr2);
> +       reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
> +       writel(reg, &mxc_ccm->cscmr2);
> +
>         reg = readl(&mxc_ccm->chsccdr);
>         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
>                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
> +       reg |= (CHSCCDR_CLK_SEL_LDB_DI0
> +               << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
>         writel(reg, &mxc_ccm->chsccdr);
> +
> +       reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
> +            | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
> +            | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
> +            | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
> +            | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
> +            | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
> +            | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
> +            | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
> +            | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
> +       writel(reg, &iomux->gpr[2]);
> +
> +       reg = readl(&iomux->gpr[3]);
> +       reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
> +                       | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
> +           | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
> +              << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
> +       writel(reg, &iomux->gpr[3]);

,and also set a lot of LDB related registers.

So I am confused here.