[U-Boot] [PATCH 1/2] mtd: nand: am335x_spl_bch.c: Fix problem with NAND_CMD_RNDOUT

[Stefan Roese]

From: Marek Belisko <marek.belisko at gmail.com>

On some NAND devices (e.g. Hynix H27U2G8F2CTR-BI on Siemens DXR2 /
Draco boards) the SPL issues the following bit-flip error messages:

nand: bit-flip corrected @oob=0
...

This patch makes sure that only the required address cycles are sent
to the NAND chip.

The same issue has been reported by Bacem Daassi:

http://e2e.ti.com/support/arm/sitara_arm/f/791/t/259699.aspx

"
The issue is mainly due to a NAND protocol violation in the omap driver since
the Random Data Output command (05h-E0h) expects to see only the column address
that should be addressed within the already loaded read page into the read
buffer. Only 2 address cycles with ALE active should be provided between the
05h and E0h commands. The Page read command expects the full address footprint
(2bytes for column address + 3bytes for row address), but once the page is
loaded into the read buffer, Random Data Output should be used with only 2bytes
for column address.
"

Signed-off-by: Marek Belisko <marek.belisko at gmail.com>
Signed-off-by: Stefan Roese <sr at denx.de>
Tested-by: Samuel Egli <samuel.egli at siemens.com>
Cc: Pekon Gupta <pekon at ti.com>
Cc: Scott Wood <scottwood at freescale.com>
---
 drivers/mtd/nand/am335x_spl_bch.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/mtd/nand/am335x_spl_bch.c b/drivers/mtd/nand/am335x_spl_bch.c
index c84851b..dd76149 100644
--- a/drivers/mtd/nand/am335x_spl_bch.c
+++ b/drivers/mtd/nand/am335x_spl_bch.c
@@ -64,14 +64,18 @@ static int nand_command(int block, int page, uint32_t offs,
 		       NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
 	hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
 	/* Row address */
-	hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
-	hwctrl(&mtd, ((page_addr >> 8) & 0xff),
+
+	if (cmd != NAND_CMD_RNDOUT) {
+		hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
+		hwctrl(&mtd, ((page_addr >> 8) & 0xff),
 		       NAND_CTRL_ALE); /* A[27:20] */
 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
-	/* One more address cycle for devices > 128MiB */
-	hwctrl(&mtd, (page_addr >> 16) & 0x0f,
+		/* One more address cycle for devices > 128MiB */
+		hwctrl(&mtd, (page_addr >> 16) & 0x0f,
 		       NAND_CTRL_ALE); /* A[31:28] */
 #endif
+	}
+
 	hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 
 	if (cmd == NAND_CMD_READ0) {
-- 
1.9.2