[U-Boot] [PATCH] arm64: zero cntvoff_el2

[fenghua at phytium.com.cn]

> Currently cntvoff_el2 is initialised with an arbitrary bag of bits
> derived from the initial value of cnthctl_el2 on the current CPU. This is
> somewhat odd and problematic as some of these bits are UNKNOWN at reset
> and may differ across CPUs (which may cause an OS at EL1 to observe time
> going backwards across CPUs).
> 
> This patch instead initialises cntvoff_el2 with xzr, giving the register
> a consistent value of zero on all CPUs.
> 
> Signed-off-by: Mark Rutland <mark.rutland at arm.com>
> Acked-by: Marc Zyngier <marc.zyngier at arm.com>
> Acked-by: Catalin Marinas <catalin.marinas at arm.com>
> Cc: Scott Wood <scottwood at freescale.com>
> Cc: David Feng <fenghua at phytium.com.cn>
> Cc: Tom Rini <trini at ti.com>
> ---
> arch/arm/cpu/armv8/transition.S | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/cpu/armv8/transition.S b/arch/arm/cpu/armv8/transition.S
> index e0a5946..38dea5c 100644
> --- a/arch/arm/cpu/armv8/transition.S
> +++ b/arch/arm/cpu/armv8/transition.S
> @@ -43,7 +43,7 @@ ENTRY(armv8_switch_to_el1)
> 	mrs	x0, cnthctl_el2
> 	orr	x0, x0, #0x3		/* Enable EL1 access to timers */
> 	msr	cnthctl_el2, x0
> -	msr	cntvoff_el2, x0
> +	msr	cntvoff_el2, xzr
> 	mrs	x0, cntkctl_el1
> 	orr	x0, x0, #0x3		/* Enable EL0 access to timers */
> 	msr	cntkctl_el1, x0
> -- 
> 1.9.1
> 
Acked-by: David.Feng <fenghua at phytium.com.cn>