[U-Boot] [PATCH v1 2/4] spi, spi_mxc: do not hang in spi_xchg_single

[Jagan Teki]

On Wed, May 28, 2014 at 3:46 PM, Heiko Schocher <hs at denx.de> wrote:
> if status register do never set MXC_CSPICTRL_TC, spi_xchg_single
> endless loops. Add a timeout here to prevent endless hang.
>
> Signed-off-by: Heiko Schocher <hs at denx.de>
> Cc: Dirk Behme <dirk.behme at gmail.com>
> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki at gmail.com>
> ---
>  drivers/spi/mxc_spi.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
> index f3f029d..3cd93cf 100644
> --- a/drivers/spi/mxc_spi.c
> +++ b/drivers/spi/mxc_spi.c
> @@ -212,6 +212,7 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
>         int nbytes = DIV_ROUND_UP(bitlen, 8);
>         u32 data, cnt, i;
>         struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
> +       int timeout;
>
>         debug("%s: bitlen %d dout 0x%x din 0x%x\n",
>                 __func__, bitlen, (u32)dout, (u32)din);
> @@ -272,9 +273,12 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
>         reg_write(&regs->ctrl, mxcs->ctrl_reg |
>                 MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);
>
> +       timeout = 10000;
>         /* Wait until the TC (Transfer completed) bit is set */
> -       while ((reg_read(&regs->stat) & MXC_CSPICTRL_TC) == 0)
> -               ;
> +       while (timeout && ((reg_read(&regs->stat) & MXC_CSPICTRL_TC) == 0)) {
> +               timeout--;
> +               udelay(10);
> +       }

Advice:
Not to use fixed time timeouts, instead go for timer api's to poll
till TC bit is set.

Sample: from zynq_spi.c
              /* Check TX FIFO completion */
                ts = get_timer(0);
                status = readl(&zslave->base->isr);
                while (!(status & ZYNQ_SPI_IXR_TXOW_MASK)) {
                        if (get_timer(ts) > CONFIG_SYS_ZYNQ_SPI_WAIT) {
                                printf("spi_xfer: Timeout! TX FIFO not full\n");
                                return -1;
                        }
                        status = readl(&zslave->base->isr);
                }

May be you can try similarly like above if possible - comments.

>
>         /* Transfer completed, clear any pending request */
>         reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
> --
> 1.8.3.1
>

thanks!
-- 
Jagan.