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Setting FPGA register brdcfg9 EPHY2 bits to '0' to initialize EPHY2 clock to RGMII mode.

Signed-off-by: Vijay Rai <vijay.rai at freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
---
 board/freescale/t1040qds/eth.c            |    4 +++-
 board/freescale/t1040qds/t1040qds_qixis.h |    4 ++++
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/board/freescale/t1040qds/eth.c b/board/freescale/t1040qds/eth.c
index 3077b4a..1929bba 100644
--- a/board/freescale/t1040qds/eth.c
+++ b/board/freescale/t1040qds/eth.c
@@ -355,7 +355,9 @@ static void set_brdcfg9_for_gtx_clk(void)
 {
 	u8 brdcfg9;
 	brdcfg9 = QIXIS_READ(brdcfg[9]);
-	brdcfg9 |= (1 << 5);
+/* Initializing EPHY2 clock to RGMII mode */
+	brdcfg9 &= ~(BRDCFG9_EPHY2_MASK);
+	brdcfg9 |= (BRDCFG9_EPHY2_VAL);
 	QIXIS_WRITE(brdcfg[9], brdcfg9);
 }
 
diff --git a/board/freescale/t1040qds/t1040qds_qixis.h b/board/freescale/t1040qds/t1040qds_qixis.h
index 98d2d39..cef8ad0 100644
--- a/board/freescale/t1040qds/t1040qds_qixis.h
+++ b/board/freescale/t1040qds/t1040qds_qixis.h
@@ -17,6 +17,10 @@
 #define BRDCFG5_IMX_MASK		0xC0
 #define BRDCFG5_IMX_DIU			0x80
 
+/* BRDCFG9[2] controls EPHY2 Clock */
+#define BRDCFG9_EPHY2_MASK              0x20
+#define BRDCFG9_EPHY2_VAL               0x00
+
 /* BRDCFG15[3] controls LCD Panel Powerdown*/
 #define BRDCFG15_LCDPD_MASK		0x10
 #define BRDCFG15_LCDPD_ENABLED		0x00
-- 
1.7.9.5