[U-Boot] [PATCH v1 3/3] sparc: Add support for gr712rc-board
Francois Retief
fgretief at spaceteq.co.za
Wed Nov 5 13:30:53 CET 2014
Add support of the Aeroflex Gaisler GR712RC-BOARD Development Kit.
Signed-off-by: Francois Retief <fgretief at spaceteq.co.za>
---
arch/sparc/Kconfig | 8 +
board/gaisler/gr712rc_board/Kconfig | 9 +
board/gaisler/gr712rc_board/MAINTAINERS | 6 +
board/gaisler/gr712rc_board/Makefile | 8 +
board/gaisler/gr712rc_board/README | 24 ++
board/gaisler/gr712rc_board/gr712rc_board.c | 68 ++++++
common/cmd_bdinfo.c | 4 +
configs/gr712rc_board_defconfig | 3 +
include/configs/gr712rc_board.h | 333 ++++++++++++++++++++++++++++
9 files changed, 463 insertions(+)
create mode 100644 board/gaisler/gr712rc_board/Kconfig
create mode 100644 board/gaisler/gr712rc_board/MAINTAINERS
create mode 100644 board/gaisler/gr712rc_board/Makefile
create mode 100644 board/gaisler/gr712rc_board/README
create mode 100644 board/gaisler/gr712rc_board/gr712rc_board.c
create mode 100644 configs/gr712rc_board_defconfig
create mode 100644 include/configs/gr712rc_board.h
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index 2df09b2..fa0e5bf 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -35,6 +35,13 @@ config TARGET_GR_XC3S_1500
bool "Gaisler GR-XC3S-1500 spartan board"
select LEON3
+config TARGET_GR712RC_BOARD
+ bool "Gaisler GR712RC-BOARD Development Kit"
+ select LEON3
+ help
+ Aeroflex Gaisler's GR712RC development board, based on the Gaisler
+ GR712RC dual-core 32-bit fault tolerant LEON3FT SPARC v8 processor.
+
config TARGET_GRSIM
bool "GRSIM simulating a LEON3 GR-XC3S-1500 board"
select LEON3
@@ -54,6 +61,7 @@ config SYS_VENDOR
source "board/gaisler/gr_cpci_ax2000/Kconfig"
source "board/gaisler/gr_ep2s60/Kconfig"
source "board/gaisler/gr_xc3s_1500/Kconfig"
+source "board/gaisler/gr712rc_board/Kconfig"
source "board/gaisler/grsim/Kconfig"
source "board/gaisler/grsim_leon2/Kconfig"
diff --git a/board/gaisler/gr712rc_board/Kconfig b/board/gaisler/gr712rc_board/Kconfig
new file mode 100644
index 0000000..4ef60e2
--- /dev/null
+++ b/board/gaisler/gr712rc_board/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_GR712RC_BOARD
+
+config SYS_BOARD
+ default "gr712rc_board"
+
+config SYS_CONFIG_NAME
+ default "gr712rc_board"
+
+endif
diff --git a/board/gaisler/gr712rc_board/MAINTAINERS b/board/gaisler/gr712rc_board/MAINTAINERS
new file mode 100644
index 0000000..1a77f89
--- /dev/null
+++ b/board/gaisler/gr712rc_board/MAINTAINERS
@@ -0,0 +1,6 @@
+GR712RC BOARD
+#M: -
+S: Maintained
+F: board/gaisler/gr712rc_board/
+F: include/configs/gr712rc_board.h
+F: configs/gr712rc_board_defconfig
diff --git a/board/gaisler/gr712rc_board/Makefile b/board/gaisler/gr712rc_board/Makefile
new file mode 100644
index 0000000..11861ef
--- /dev/null
+++ b/board/gaisler/gr712rc_board/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2014, Denel Spaceteq
+# Francois Retief <fgretief at spaceteq.co.za>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := gr712rc_board.o
diff --git a/board/gaisler/gr712rc_board/README b/board/gaisler/gr712rc_board/README
new file mode 100644
index 0000000..1f2efab
--- /dev/null
+++ b/board/gaisler/gr712rc_board/README
@@ -0,0 +1,24 @@
+These jumpers need to be correctly set for U-Boot to operate.
+
+Jumpers for SDRAM:
+ JP12 = C SDCSN0
+ JP13 = C SDCSN1
+ JP24 = C SDDQM0
+ JP25 = C SDDQM1
+ JP48 = C SDCASN
+ JP49 = C SDRASN
+ JP52 = C SDWEN
+ JP53 = C SDDQM2
+ JP54 = C SDDQM3
+
+Jumpers for Ethernet (RMII):
+ JP28 = F RMTXD0
+ JP29 = F RMTXD1
+ JP30 = F RMRXD0
+ JP31 = F RMRXD1
+ JP32 = F RMTXEN
+ JP34 = F RMCRSDV
+ JP35 = F RMMDINT
+ JP36 = F RMMDIO
+ JP37 = F RMMDC
+ JP38 = F RMRFCLK
diff --git a/board/gaisler/gr712rc_board/gr712rc_board.c b/board/gaisler/gr712rc_board/gr712rc_board.c
new file mode 100644
index 0000000..0b454ba
--- /dev/null
+++ b/board/gaisler/gr712rc_board/gr712rc_board.c
@@ -0,0 +1,68 @@
+/*
+ * GR712RC-BOARD Developement Kit
+ *
+ * (C) Copyright 2014, Denel Spaceteq
+ * Francois Retief <fgretief at spaceteq.co.za>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <ambapp.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ puts("Board: GR712RC-BOARD Development Kit\n");
+ return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+
+#define GAISLER_CLKGATE 0x02C
+
+#define CLKGATE_GRETH BIT(0)
+#define CLKGATE_GRSPW0 BIT(1)
+#define CLKGATE_GRSPW1 BIT(2)
+#define CLKGATE_GRSPW2 BIT(3)
+#define CLKGATE_GRSPW3 BIT(4)
+#define CLKGATE_GRSPW4 BIT(5)
+#define CLKGATE_GRSPW5 BIT(6)
+#define CLKGATE_CANCORE BIT(7)
+#define CLKGATE_SATCAN BIT(8)
+#define CLKGATE_CCSDS_TLM BIT(9)
+#define CLKGATE_CCSDS_TCM BIT(10)
+#define CLKGATE_MIL1553 BIT(11)
+
+#define BIT(x) (1<<(x))
+
+typedef struct {
+ volatile unsigned int unlock;
+ volatile unsigned int clock_enable;
+ volatile unsigned int core_reset;
+} ambapp_dev_clkgate;
+
+int board_eth_init(bd_t *bis)
+{
+ ambapp_apbdev apbdev;
+
+ if (ambapp_apb_first(VENDOR_GAISLER, GAISLER_CLKGATE, &apbdev) != 1) {
+ puts("Unable to find CLKGATE core. Clock to GRETH not enabled!\n");
+ } else {
+ ambapp_dev_clkgate *clkgate = (ambapp_dev_clkgate *) apbdev.address;
+
+ /* Enable clock for GRETH core */
+ clkgate->unlock = CLKGATE_GRETH;
+ clkgate->core_reset = CLKGATE_GRETH;
+ clkgate->clock_enable = CLKGATE_GRETH;
+ clkgate->core_reset = 0;
+ clkgate->unlock = 0;
+ }
+
+ return cpu_eth_init(bis);
+}
+
+#endif
diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index 3d37a86..6af5afe 100644
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
@@ -216,10 +216,14 @@ int do_bdinfo(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
print_num("flashstart ", bd->bi_flashstart);
print_num("CONFIG_SYS_MONITOR_BASE ", CONFIG_SYS_MONITOR_BASE);
print_num("CONFIG_ENV_ADDR ", CONFIG_ENV_ADDR);
+#ifdef CONFIG_SYS_RELOC_MONITOR_BASE
printf("CONFIG_SYS_RELOC_MONITOR_BASE = 0x%x (%d)\n", CONFIG_SYS_RELOC_MONITOR_BASE,
CONFIG_SYS_MONITOR_LEN);
+#endif
+#ifdef CONFIG_SYS_MALLOC_BASE
printf("CONFIG_SYS_MALLOC_BASE = 0x%x (%d)\n", CONFIG_SYS_MALLOC_BASE,
CONFIG_SYS_MALLOC_LEN);
+#endif
printf("CONFIG_SYS_INIT_SP_OFFSET = 0x%x (%d)\n", CONFIG_SYS_INIT_SP_OFFSET,
CONFIG_SYS_STACK_SIZE);
printf("CONFIG_SYS_PROM_OFFSET = 0x%x (%d)\n", CONFIG_SYS_PROM_OFFSET,
diff --git a/configs/gr712rc_board_defconfig b/configs/gr712rc_board_defconfig
new file mode 100644
index 0000000..c3c0a93
--- /dev/null
+++ b/configs/gr712rc_board_defconfig
@@ -0,0 +1,3 @@
+CONFIG_SYS_TEXT_BASE=0x60000000
+CONFIG_SPARC=y
+CONFIG_TARGET_GR712RC_BOARD=y
diff --git a/include/configs/gr712rc_board.h b/include/configs/gr712rc_board.h
new file mode 100644
index 0000000..afccf01
--- /dev/null
+++ b/include/configs/gr712rc_board.h
@@ -0,0 +1,333 @@
+/* Configuration header file for GR712RC-BOARD Development Kit
+ *
+ * (C) Copyright 2007
+ * Daniel Hellstrom, Gaisler Research, daniel at gaisler.com.
+ *
+ * (C) Copyright 2014
+ * Francois Retief, Denel Spaceteq, fgretief at spaceteq.co.za.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H__
+#define __CONFIG_H__
+
+#include <linux/sizes.h>
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* CPU / AMBA BUS configuration */
+#define CONFIG_SYS_CLK_FREQ 80000000 /* 80MHz (JP84=CLK2, DLLBPN=0) */
+
+/* Number of SPARC register windows */
+#define CONFIG_SYS_SPARC_NWINDOWS 8
+
+/* GR712RC SoC has two SPARC processors */
+#define CONFIG_SMP
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/* Partitions */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/*
+ * Supported commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_BDI /* bdinfo */
+#define CONFIG_CMD_BOOTD /* bootd */
+#define CONFIG_CMD_CONSOLE /* coninfo */
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_ECHO /* echo arguments */
+#define CONFIG_CMD_FLASH /* flinfo, erase, protect */
+#define CONFIG_CMD_IMI /* iminfo */
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ITEST /* Integer (and string) test */
+#define CONFIG_CMD_LOADB /* loadb */
+#define CONFIG_CMD_LOADS /* loads */
+#define CONFIG_CMD_MEMINFO /* meminfo */
+#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop */
+#define CONFIG_CMD_MEMTEST /* mtest */
+#define CONFIG_CMD_MII /* MII support */
+#define CONFIG_CMD_MISC /* Misc functions like sleep etc */
+#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
+#define CONFIG_CMD_PING /* ping support */
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_RUN /* run command in env variable */
+#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
+#define CONFIG_CMD_SOURCE /* "source" command support */
+
+/* Autobooting */
+#define CONFIG_BOOTDELAY -1 /* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+/*#define CONFIG_SYS_HUSH_PARSER 0*/
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath},nfsvers=4,tcp\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "flash_nfs=run nfsargs addip;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0" \
+ "scratch=40000000\0" \
+ "getkernel=tftpboot $(scratch) $(bootfile)\0" \
+ ""
+#define CONFIG_IPADDR 10.24.5.199
+#define CONFIG_NETMASK 255.255.0.0
+#define CONFIG_GATEWAYIP 10.24.49.1
+#define CONFIG_SERVERIP 10.24.5.54
+#define CONFIG_ROOTPATH "/srv/nfsroot/gr712rc-board"
+#define CONFIG_HOSTNAME gr712rc-board
+#define CONFIG_BOOTFILE "/uImage"
+#define CONFIG_LOADADDR 0x40000000
+#define CONFIG_ETHADDR 00:00:7a:cc:00:12
+
+#define CONFIG_BOOTARGS "console=ttyS0,115200 ip=dhcp root=/dev/nfs rw nfsroot=10.24.5.54:/srv/nfsroot/gr712rc-board,nfsvers=4,tcp"
+#define CONFIG_BOOTCOMMAND "tftpboot; bootm"
+
+/* Memory MAP
+ *
+ * Flash:
+ * |--------------------------------|
+ * | 0x00000000 Text & Data & BSS | *
+ * | for Monitor | *
+ * | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| *
+ * | UNUSED / Growth | * 256kb
+ * |--------------------------------|
+ * | 0x00050000 Base custom area | *
+ * | kernel / FS | *
+ * | | * Rest of Flash
+ * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|
+ * | END-0x00008000 Environment | * 32kb
+ * |--------------------------------|
+ *
+ *
+ *
+ * Main Memory:
+ * |--------------------------------|
+ * | UNUSED / scratch area |
+ * | |
+ * | |
+ * | |
+ * | |
+ * |--------------------------------|
+ * | Monitor .Text / .DATA / .BSS | * 256kb
+ * | Relocated! | *
+ * |--------------------------------|
+ * | Monitor Malloc | * 128kb (contains relocated environment)
+ * |--------------------------------|
+ * | Monitor/kernel STACK | * 64kb
+ * |--------------------------------|
+ * | Page Table for MMU systems | * 2k
+ * |--------------------------------|
+ * | PROM Code accessed from Linux | * 6kb-128b
+ * |--------------------------------|
+ * | Global data (avail from kernel)| * 128b
+ * |--------------------------------|
+ *
+ */
+
+/*
+ * Flash configuration
+ */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+#define CONFIG_SYS_FLASH_BASE 0x00000000
+#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MiB */
+#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
+#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+//#define CONFIG_FLASH_SHOW_PROGRESS 45
+#define CONFIG_FLASH_VERIFY
+
+#undef CONFIG_SYS_NO_FLASH
+
+/*
+ * Environment settings
+ */
+#define CONFIG_CMD_SAVEENV
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128 KiB */
+#define CONFIG_ENV_SIZE 0x8000 /* 32 KiB */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SECT_SIZE)
+
+#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
+
+/* #define CONFIG_ENV_IS_NOWHERE 1 */
+
+/*
+ * Memory map
+ */
+#if 0 /* SRAM and SDRAM */
+
+#define CONFIG_SYS_SRAM_BASE 0x40000000
+#define CONFIG_SYS_SRAM_SIZE 0x00800000 /* 8 MiB */
+#define CONFIG_SYS_SRAM_END (CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE)
+
+#define CONFIG_SYS_SDRAM_BASE 0x60000000
+#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 MiB */
+#define CONFIG_SYS_SDRAM_END (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE)
+
+#define CONFIG_SYS_OCRAM_BASE 0xA0000000
+#define CONFIG_SYS_OCRAM_SIZE 0x00030000 /* 192 KiB */
+#define CONFIG_SYS_OCRAM_END (CONFIG_SYS_OCRAM_BASE + CONFIG_SYS_OCRAM_SIZE)
+/* Note: Configuration register at 0x80100000 for OCRAM */
+
+/* Always Run U-Boot from SRAM */
+#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
+#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
+
+#else /* SDRAM only */
+
+#undef CONFIG_SYS_SRAM_BASE
+#undef CONFIG_SYS_SRAM_SIZE
+#undef CONFIG_SYS_SRAM_END
+
+#define CONFIG_SYS_SDRAM_BASE 0x60000000
+#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 MiB */
+#define CONFIG_SYS_SDRAM_END (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE)
+
+#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
+#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
+
+#endif
+
+/*#define CONFIG_NR_DRAM_BANKS 1 |* we have 1 bank of SDRAM */
+#undef CONFIG_NR_DRAM_BANKS
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_RAM_END - GENERATED_GBL_DATA_SIZE)
+/*#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_SRAM_END - GENERATED_GBL_DATA_SIZE)*/
+/*#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_OCRAM_END - GENERATED_GBL_DATA_SIZE)*/
+/*#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET*/
+#define CONFIG_SYS_INIT_SP_OFFSET (0xA0000000 + 0x00030000 - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_PROM_SIZE (8192-GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_PROM_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
+
+//#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_PROM_OFFSET-32)
+#define CONFIG_SYS_STACK_SIZE (0x10000-32)
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+# define CONFIG_SYS_RAMBOOT 1
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+#ifndef CONFIG_SYS_GENERIC_BOARD
+
+#define CONFIG_SYS_MALLOC_END (CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE)
+#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN)
+
+/* relocated monitor area */
+#define CONFIG_SYS_RELOC_MONITOR_MAX_END CONFIG_SYS_MALLOC_BASE
+#define CONFIG_SYS_RELOC_MONITOR_BASE (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)
+
+/* make un relocated address from relocated address */
+#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE))
+
+#endif
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_GRETH 1 /* Aeroflex Gaisler GRETH driver */
+#define CONFIG_MII 1 /* MII PHY management */
+
+/*#define CONFIG_PHY_NATSEMI |* board has DP83848C chip */
+
+/* Default HARDWARE address */
+#define GRETH_HWADDR_0 0x00
+#define GRETH_HWADDR_1 0x00
+#define GRETH_HWADDR_2 0x7A
+#define GRETH_HWADDR_3 0xcc
+#define GRETH_HWADDR_4 0x00
+#define GRETH_HWADDR_5 0x12
+
+/*
+ * Define CONFIG_GRETH_10MBIT to force GRETH at 10Mb/s
+ */
+/* #define CONFIG_GRETH_10MBIT 1 */
+#define CONFIG_SYS_GRLIB_GRETH_PHYADDR 0x01 /* DP83848C chip on address 0x01 */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* memtest works on 64MiB SDRAM */
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 4 * SZ_1M)
+
+#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
+
+/***** Gaisler GRLIB IP-Cores Config ********/
+
+/* Gaisler Fault Tolerant Memory controller */
+#define CONFIG_SYS_GRLIB_FT_MEMCFG1 (0x0803c0ff | (1<<11))
+#define CONFIG_SYS_GRLIB_FT_MEMCFG2 0x9a205465
+#define CONFIG_SYS_GRLIB_FT_MEMCFG3 0x08266010
+
+/* System information about memory from GRMON
+ *
+ * grmon2> info sys mctrl0
+ * mctrl0 Aeroflex Gaisler Memory controller with EDAC
+ * AHB: 00000000 - 20000000
+ * AHB: 20000000 - 40000000
+ * AHB: 40000000 - 80000000
+ * APB: 80000000 - 80000100
+ * 8-bit prom @ 0x00000000
+ * 32-bit static ram: 1 * 8192 kbyte @ 0x40000000
+ * 32-bit sdram: 2 * 64 Mbyte @ 0x60000000
+ * col 9, cas 2, ref 7.8 us
+ *
+ * grmon2> mcfg1; mcfg2; mcfg3
+ * mcfg1: 0x0803c0ff
+ * mcfg2: 0x9a205465
+ * mcfg3: 0x08266010
+ */
+
+/* default kernel command line */
+#define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,115200\0\0"
+
+#define CONFIG_IDENT_STRING " Gaisler GR712RC-BOARD"
+
+#endif /* __CONFIG_H */
--
1.9.3
________________________________
Disclaimer and confidentiality note – refer to our website for further details: www.spaceteq.co.za <http://www.spaceteq.co.za/home/emaildisclaimer/>
More information about the U-Boot
mailing list