[U-Boot] [PATCH 0/39] x86: Add support for running on bare hardware
Simon Glass
sjg at chromium.org
Thu Nov 6 21:19:52 CET 2014
At present U-Boot's x86 support requires Coreboot to run first, starting
up the CPU and then setting up SDRAM and video among other tasks. U-Boot
then runs as a payload. Notably U-Boot does not handle the ACPI fun on
x86 where the kernel can call back into the 'BIOS' to perform certain tasks.
This Coreboot + U-Boot method is used for link (Chromebook Pixel) and it
works fairly well.
However this does not remove the need for all x86-specific init in U-Boot.
For each generation of chipset we need to adjust U-Boot to make it work,
albeit sometimes not a lot. In any case this work has not been done so the
x86 port risks being stranded.
There are also a few disadvantages to using two separate boot loaders. When
Coreboot decides not set to up the video card, it is not possible for U-Boot
to go back and do this.
Building an image which has both boot loaders in itis a little tricky,
particularly with the binary blobs that are required.
After some experimentation prompted by a discussion at ELCE, it was found
that while x86 is somewhat different to most of the other architectures that
U-Boot supports, it actually fits the model fairly well. There is nothing
magic about getting the platform running. Also it turns out that x86 likes
running before relocation with no DRAM, using global_data, relocating and
then starting up the full U-Boot, all within the same image (Coreboot
splits this into three programs which run one after the other). Perhaps
this is because U-Boot was conceived before the more modern SoCs with SRAM,
FAT file system code in the ROM, etc.
This series contains a basic port of U-Boot to a bare x86 environment. It
would be targeted at some generally available board, such as the Minnowmax,
except that it doesn't seem to be generally available, at least for me. So
while that remains a goal, for now the port targets link. It is already
supported in U-Boot and the platform is well understood.
The following are implemented in this series:
- ivybridge support with some peripherals enabled
- SDRAM init using a binary blob (Memory Reference Code)
- Use of Intel Management Engine via another binary blob
- microcode update from device tree
- ifttool for creating ROMs of the required format (u-boot.rom)
- GPIO
Notably missing are:
- PCI device support (USB, SATA)
- Video support
- MTRR setup (for performance)
- Real time clock
- Chrome OS EC
- Documentation
- Links to binary blobs
These will be addressed in a follow-up series. Things like ACPI and SMI will
come later.
Unfortunately this series is quite long as it includes basic infrastructure
needed on x86. But it is a solid step forward: with this series, link boots
to a prompt.
This series is available at u-boot-x86/working
Simon Glass (39):
Move early malloc() to before arch_cpu_init()
fdt: Add a function to decode a variable-sized u32 array
dm: serial: Move current serial port pointer to global_data
dm: gpio: Add a function to read an ID from a list of GPIOs
x86: Add ifdtool for working with Intel Flash Descriptor ROM images
x86: config: Move common x86 configs to a common file
x86: Add processor functions for cpuid and stack pointer
x86: Remove REALMODE_BASE which is no longer used
x86: Remove board_init16() call which is not used
x86: Remove unused early_board_init() call
x86: Invalidate TLB as early as possible
x86: Tidy up global descriptor table setup
x86: Use the standard dram_init() function
x86: Use the standard arch_cpu_init() function
x86: Remove unnecessary find_fdt() function
x86: Fix up some missing prototypes
x86: Add chromebook_link board
x86: Save the BIST value on reset
x86: Build a .rom file which can be flashed to an x86 machine
x86: Emit post codes in startup code
x86: chromebook_link: Implement CAR support (cache as RAM)
x86: Move Coreboot PCI into common cpu area
x86: Refactor PCI to permit alternate init
x86: ivybridge: Enable PCI in early init
x86: pci: Allow configuration before relocation
x86: ivybridge: Add early LPC init so that serial works
x86: Tidy up coreboot header usage
x86: Add clr/setbits functions
x86: Add msr read/write functions that use a structure
x86: ivybridge: Perform initial CPU setup
x86: ivybridge: Check BIST value on boot
x86: ivybridge: Perform Intel microcode update on boot
RFC: x86: dts: Add microcode updates for ivybridge CPU
x86: ivybridge: Add early init for PCH devices
x86: ivybridge: Add support for early GPIO init
x86: chromebook_link: Enable GPIO support
x86: Make show_boot_progress() common
x86: ivybridge: Add LAPIC support
x86: ivybridge: Implement SDRAM init
Makefile | 32 +-
arch/x86/Kconfig | 54 ++
arch/x86/config.mk | 1 -
arch/x86/cpu/Makefile | 1 +
arch/x86/cpu/coreboot/Makefile | 1 -
arch/x86/cpu/coreboot/coreboot.c | 44 +-
arch/x86/cpu/coreboot/ipchecksum.c | 2 +-
arch/x86/cpu/coreboot/pci.c | 49 -
arch/x86/cpu/coreboot/sdram.c | 15 +-
arch/x86/cpu/coreboot/tables.c | 6 +-
arch/x86/cpu/cpu.c | 60 +-
arch/x86/cpu/interrupts.c | 2 +-
arch/x86/cpu/ivybridge/Kconfig | 157 ++++
arch/x86/cpu/ivybridge/Makefile | 15 +
arch/x86/cpu/ivybridge/car.S | 174 ++++
arch/x86/cpu/ivybridge/cpu.c | 356 +++++++
arch/x86/cpu/ivybridge/early_init.c | 145 +++
arch/x86/cpu/ivybridge/early_me.c | 191 ++++
arch/x86/cpu/ivybridge/lpc.c | 48 +
arch/x86/cpu/ivybridge/me_status.c | 195 ++++
arch/x86/cpu/ivybridge/microcode_intel.c | 150 +++
arch/x86/cpu/ivybridge/report_platform.c | 98 ++
arch/x86/cpu/ivybridge/sdram.c | 571 +++++++++++
arch/x86/cpu/pci.c | 150 +++
arch/x86/cpu/start.S | 66 +-
arch/x86/cpu/start16.S | 18 +-
arch/x86/dts/Makefile | 1 +
arch/x86/dts/chromebook_link.dts | 1 +
arch/x86/dts/link.dts | 127 ++-
arch/x86/dts/m12206a7_00000028.dtsi | 622 ++++++++++++
arch/x86/dts/m12306a9_00000017.dtsi | 750 +++++++++++++++
arch/x86/include/asm/arch-coreboot/gpio.h | 5 -
arch/x86/include/asm/arch-ivybridge/gpio.h | 10 +
arch/x86/include/asm/arch-ivybridge/me.h | 357 +++++++
arch/x86/include/asm/arch-ivybridge/microcode.h | 20 +
arch/x86/include/asm/arch-ivybridge/model_206ax.h | 82 ++
arch/x86/include/asm/arch-ivybridge/pch.h | 356 +++++++
arch/x86/include/asm/arch-ivybridge/pei_data.h | 121 +++
arch/x86/include/asm/arch-ivybridge/sandybridge.h | 109 +++
arch/x86/include/asm/config.h | 1 +
arch/x86/include/asm/global_data.h | 24 +
arch/x86/include/asm/gpio.h | 142 ++-
arch/x86/include/asm/init_helpers.h | 1 -
arch/x86/include/asm/io.h | 49 +
arch/x86/include/asm/lapic.h | 59 ++
arch/x86/include/asm/lapic_def.h | 101 ++
arch/x86/include/asm/msr.h | 19 +
arch/x86/include/asm/mtrr.h | 121 +++
arch/x86/include/asm/pci.h | 13 +
arch/x86/include/asm/post.h | 50 +
arch/x86/include/asm/processor.h | 135 +++
arch/x86/include/asm/u-boot-x86.h | 19 +-
arch/x86/lib/Makefile | 1 +
arch/x86/lib/ramtest.c | 79 ++
board/chromebook-x86/coreboot/Makefile | 2 +-
board/chromebook-x86/coreboot/coreboot_start.S | 13 -
board/google/chromebook_link/Kconfig | 31 +
board/google/chromebook_link/MAINTAINERS | 6 +
board/google/chromebook_link/Makefile | 15 +
board/google/chromebook_link/link.c | 124 +++
common/board_f.c | 14 +-
configs/chromebook_link_defconfig | 10 +
doc/device-tree-bindings/misc/intel-lpc.txt | 23 +
drivers/gpio/gpio-uclass.c | 19 +
drivers/gpio/intel_ich6_gpio.c | 79 +-
drivers/serial/serial-uclass.c | 35 +-
include/asm-generic/global_data.h | 1 +
include/asm-generic/gpio.h | 11 +-
include/configs/chromebook_link.h | 68 ++
include/configs/coreboot.h | 289 +-----
include/configs/x86-common.h | 272 ++++++
include/fdtdec.h | 18 +
lib/asm-offsets.c | 3 +
lib/fdtdec.c | 22 +
tools/Makefile | 2 +
tools/ifdtool.c | 1039 +++++++++++++++++++++
tools/ifdtool.h | 88 ++
77 files changed, 7690 insertions(+), 470 deletions(-)
delete mode 100644 arch/x86/cpu/coreboot/pci.c
create mode 100644 arch/x86/cpu/ivybridge/Kconfig
create mode 100644 arch/x86/cpu/ivybridge/Makefile
create mode 100644 arch/x86/cpu/ivybridge/car.S
create mode 100644 arch/x86/cpu/ivybridge/cpu.c
create mode 100644 arch/x86/cpu/ivybridge/early_init.c
create mode 100644 arch/x86/cpu/ivybridge/early_me.c
create mode 100644 arch/x86/cpu/ivybridge/lpc.c
create mode 100644 arch/x86/cpu/ivybridge/me_status.c
create mode 100644 arch/x86/cpu/ivybridge/microcode_intel.c
create mode 100644 arch/x86/cpu/ivybridge/report_platform.c
create mode 100644 arch/x86/cpu/ivybridge/sdram.c
create mode 100644 arch/x86/cpu/pci.c
create mode 120000 arch/x86/dts/chromebook_link.dts
create mode 100644 arch/x86/dts/m12206a7_00000028.dtsi
create mode 100644 arch/x86/dts/m12306a9_00000017.dtsi
create mode 100644 arch/x86/include/asm/arch-ivybridge/gpio.h
create mode 100644 arch/x86/include/asm/arch-ivybridge/me.h
create mode 100644 arch/x86/include/asm/arch-ivybridge/microcode.h
create mode 100644 arch/x86/include/asm/arch-ivybridge/model_206ax.h
create mode 100644 arch/x86/include/asm/arch-ivybridge/pch.h
create mode 100644 arch/x86/include/asm/arch-ivybridge/pei_data.h
create mode 100644 arch/x86/include/asm/arch-ivybridge/sandybridge.h
create mode 100644 arch/x86/include/asm/lapic.h
create mode 100644 arch/x86/include/asm/lapic_def.h
create mode 100644 arch/x86/include/asm/mtrr.h
create mode 100644 arch/x86/include/asm/post.h
create mode 100644 arch/x86/lib/ramtest.c
delete mode 100644 board/chromebook-x86/coreboot/coreboot_start.S
create mode 100644 board/google/chromebook_link/Kconfig
create mode 100644 board/google/chromebook_link/MAINTAINERS
create mode 100644 board/google/chromebook_link/Makefile
create mode 100644 board/google/chromebook_link/link.c
create mode 100644 configs/chromebook_link_defconfig
create mode 100644 doc/device-tree-bindings/misc/intel-lpc.txt
create mode 100644 include/configs/chromebook_link.h
create mode 100644 include/configs/x86-common.h
create mode 100644 tools/ifdtool.c
create mode 100644 tools/ifdtool.h
--
2.1.0.rc2.206.gedb03e5
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