[U-Boot] [PATCH 3/6] spi: Add designware master SPI DM driver used on SoCFPGA

[Marek Vasut]

On Friday, November 07, 2014 at 01:50:31 PM, Stefan Roese wrote:
> This patch adds the driver for the Designware master SPI controller. This
> IP core is integrated on the Altera SoCFPGA. This implementation is a
> driver model (DM) implementation. So multiple SPI drivers can be used.
> Thats necessary, since SoCFPGA also integrates the Cadence QSPI controller
> used to connect the SPI NOR flashes. Without DM, using multiple SPI
> driver is not possible.
> 
> This driver is very loosly based on the Linux driver. Most of the Linux
> driver is removed. Only the polling loop for the transfer is really used
> from this driver. As we don't support interrupts and DMA right now.
> 
> This is tested on the SoCrates SoCFPGA board using the SPI pins on the
> P14 header.
> 
> Signed-off-by: Stefan Roese <sr at denx.de>
> Cc: Chin Liang See <clsee at altera.com>
> Cc: Dinh Nguyen <dinguyen at altera.com>
> Cc: Vince Bridgers <vbridger at altera.com>
> Cc: Marek Vasut <marex at denx.de>
> Cc: Pavel Machek <pavel at denx.de>
> Cc: Simon Glass <sjg at chromium.org>
> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki at gmail.com>

[...]

> diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
> new file mode 100644
> index 0000000..1bc0d04
> --- /dev/null
> +++ b/drivers/spi/designware_spi.c
> @@ -0,0 +1,425 @@
> +/*
> + * Designware master SPI core controller driver
> + *
> + * Copyright (C) 2014 Stefan Roese <sr at denx.de>
> + *
> + * Very loosly based on the Linux driver version which is:
> + * Copyright (c) 2009, Intel Corporation.
> + *
> + * SPDX-License-Identifier:	GPL-2.0

What's the agreement about the licensing now, GPL-2.0 or GPL-2.0+ ?

[...]

> +static inline u32 dw_readl(struct dw_spi_priv *priv, u32 offset)
> +{
> +	return __raw_readl(priv->regs + offset);
> +}

Do we really need these wrappers ?

[...]

Thanks!