[U-Boot] [PATCH 2/4 v4] arm: socfpga: dts: Add Cadence QSPI DT node to socfpga.dtsi

[Simon Glass]

Hi Stefan,

On 7 November 2014 04:37, Stefan Roese <sr at denx.de> wrote:
> This DT node is taken from the Rocketboard.org Linux repsitory. And
> is needed to enable (configure) the Cadence DM SPI driver.
>
> Signed-off-by: Stefan Roese <sr at denx.de>
> Cc: Chin Liang See <clsee at altera.com>
> Cc: Dinh Nguyen <dinguyen at altera.com>
> Cc: Vince Bridgers <vbridger at altera.com>
> Cc: Marek Vasut <marex at denx.de>
> Cc: Pavel Machek <pavel at denx.de>
> Cc: Simon Glass <sjg at chromium.org>
> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki at gmail.com>
> ---
>  arch/arm/dts/socfpga.dtsi                  | 15 +++++++++++++++
>  arch/arm/dts/socfpga_cyclone5_socrates.dts | 20 ++++++++++++++++++++
>  2 files changed, 35 insertions(+)
>
> diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
> index 4472fd9..4a789a9 100644
> --- a/arch/arm/dts/socfpga.dtsi
> +++ b/arch/arm/dts/socfpga.dtsi
> @@ -639,6 +639,21 @@
>                         clock-names = "biu", "ciu";
>                 };
>
> +               qspi: spi at ff705000 {
> +                       compatible = "cadence,qspi";
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       reg = <0xff705000 0x1000>,
> +                               <0xffa00000 0x1000>;
> +                       interrupts = <0 151 4>;
> +                       clocks = <&qspi_clk>;
> +                       ext-decoder = <0>;  /* external decoder */
> +                       num-chipselect = <4>;
> +                       fifo-depth = <128>;
> +                       bus-num = <2>;
> +                       status = "disabled";
> +               };
> +

Is this the same binding as Linux? Can you please bring in the binding
document too? Some of these feel like they should have a
"manufacture," prefix.


>                 /* Local timer */
>                 timer at fffec600 {
>                         compatible = "arm,cortex-a9-twd-timer";
> diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts
> index a1814b4..9277174 100644
> --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts
> +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts
> @@ -48,3 +48,23 @@
>  &mmc {
>         status = "okay";
>  };
> +
> +&qspi {
> +       status = "okay";
> +
> +       flash0: n25q00 at 0 {
> +               #address-cells = <1>;
> +               #size-cells = <1>;
> +               compatible = "n25q00";
> +               reg = <0>;      /* chip select */
> +               spi-max-frequency = <50000000>;
> +               m25p,fast-read;
> +               page-size = <256>;
> +               block-size = <16>; /* 2^16, 64KB */
> +               read-delay = <4>;  /* delay value in read data capture register */
> +               tshsl-ns = <50>;
> +               tsd2d-ns = <50>;
> +               tchsh-ns = <4>;
> +               tslch-ns = <4>;
> +       };
> +};
> --
> 2.1.3
>

Regards,
Simon