[U-Boot] [PATCH v2 32/33] x86: ivybridge: Implement SDRAM init

[Bin Meng]

Hi Simon,

On Wed, Nov 12, 2014 at 12:18 AM, Simon Glass <sjg at chromium.org> wrote:
> Hi Bin,
>
> On 11 November 2014 07:37, Bin Meng <bmeng.cn at gmail.com> wrote:
>> Hi Simon,
>>
>> I am not sure if there is anything I missed but when I look at the
>> u-boot-x86/working, the repo content does not match the patch v2 here.
>> And seems you missed my previous comments @
>> http://u-boot.10912.n7.nabble.com/PATCH-0-39-x86-Add-support-for-running-on-bare-hardware-tp194993p195356.html
>
> OK, which ones have I missed?

Does the above link not work for you? The comments were:

> +static void report_cpu_info(void)
> +{
> +       struct cpuid_result cpuidr;
> +       u32 i, index;
> +       char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */
> +       int vt, txt, aes;
> +       const char *mode[] = {"NOT ", ""};
> +
> +       index = 0x80000000;
> +       cpuidr = cpuid(index);
> +       if (cpuidr.eax < 0x80000004) {
> +               strcpy(cpu_string, "Platform info not available");
> +       } else {
> +               u32 *p = (u32 *)cpu_string;
> +               for (i = 2; i <= 4 ; i++) {
> +                       cpuidr = cpuid(index + i);
> +                       *p++ = cpuidr.eax;
> +                       *p++ = cpuidr.ebx;
> +                       *p++ = cpuidr.ecx;
> +                       *p++ = cpuidr.edx;
> +               }
> +       }
> +       /* Skip leading spaces in CPU name string */
> +       while (cpu_name[0] == ' ')
> +               cpu_name++;

The above codes can be just replaced by a call to cpu_get_name()

[snip]

> diff --git a/arch/x86/dts/link.dts b/arch/x86/dts/link.dts
> index 84fb0a9..f152da5 100644
> --- a/arch/x86/dts/link.dts
> +++ b/arch/x86/dts/link.dts
> @@ -41,6 +41,117 @@
>         chosen { };
>         memory { device_type = "memory"; reg = <0 0>; };
>
> +       spd {
> +               compatible = "memory-spd";
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +               elpida_4Gb_1600_x16 {
> +                       reg = <0>;
> +                       data = [92 10 0b 03 04 19 02 02
> +                               03 52 01 08 0a 00 fe 00
> +                               69 78 69 3c 69 11 18 81
> +                               20 08 3c 3c 01 40 83 81
> +                               00 00 00 00 00 00 00 00
> +                               00 00 00 00 00 00 00 00
> +                               00 00 00 00 00 00 00 00
> +                               00 00 00 00 0f 11 42 00
> +                               00 00 00 00 00 00 00 00
> +                               00 00 00 00 00 00 00 00
> +                               00 00 00 00 00 00 00 00
> +                               00 00 00 00 00 00 00 00
> +                               00 00 00 00 00 00 00 00
> +                               00 00 00 00 00 00 00 00
> +                               00 00 00 00 00 02 fe 00
> +                               11 52 00 00 00 07 7f 37
> +                               45 42 4a 32 30 55 47 36
> +                               45 42 55 30 2d 47 4e 2d
> +                               46 20 30 20 02 fe 00 00
> +                               00 00 00 00 00 00 00 00
> +                               00 00 00 00 00 00 00 00
> +                               00 00 00 00 00 00 00 00
> +                               00 00 00 00 00 00 00 00
> +                               00 00 00 00 00 00 00 00
> +                               00 00 00 00 00 00 00 00
> +                               00 00 00 00 00 00 00 00
> +                               00 00 00 00 00 00 00 00
> +                               00 00 00 00 00 00 00 00
> +                               00 00 00 00 00 00 00 00
> +                               00 00 00 00 00 00 00 00
> +                               00 00 00 00 00 00 00 00
> +                               00 00 00 00 00 00 00 00];
> +               };

Is this the limitation of the MRC that it cannot read SPD from the
DIMM? Or is it because the RAM chip is soldered on board?

[snip]

> diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
> index 25b672a..d0c7f30 100644
> --- a/arch/x86/lib/Makefile
> +++ b/arch/x86/lib/Makefile
> @@ -15,6 +15,7 @@ obj-$(CONFIG_SYS_PCAT_TIMER) += pcat_timer.o
>  obj-$(CONFIG_PCI) += pci_type1.o
>  obj-y  += relocate.o
>  obj-y += physmem.o
> +obj-y += ramtest.o

Can we make the ramtest wrapped by CONFIG_X86_RAMTEST?

Regards,
Bin