[U-Boot] [PATCH] powerpc/t2080: updating rcw for silicon v1.1

[Shengzhou Liu]

T2080 v1.1 requires different MEM_PLL_RAT from previous v1.0,
and also update core frequency to 1.8GHz for v1.1.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu at freescale.com>
---
 board/freescale/t208xqds/t2080_rcw.cfg |  9 +++++----
 board/freescale/t208xrdb/t2080_rcw.cfg | 13 +++++++------
 2 files changed, 12 insertions(+), 10 deletions(-)

diff --git a/board/freescale/t208xqds/t2080_rcw.cfg b/board/freescale/t208xqds/t2080_rcw.cfg
index 972dedc..b593a2d 100644
--- a/board/freescale/t208xqds/t2080_rcw.cfg
+++ b/board/freescale/t208xqds/t2080_rcw.cfg
@@ -1,8 +1,9 @@
+#For T2080 silicon v1.1 on QDS board
 #PBL preamble and RCW header
 aa55aa55 010e0100
-#SerDes Protocol: 0x66_0x16
-#Core/DDR: 1533Mhz/2133MT/s
-12100017 15000000 00000000 00000000
-66150002 00008400 e8104000 c1000000
+#SerDes Protocol: 0x66_0x15
+#Core:1800Mhz,  DDR:1867MT/s
+0c070012 0e000000 00000000 00000000
+66150002 00000000 e8104000 c1000000
 00000000 00000000 00000000 000307fc
 00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xrdb/t2080_rcw.cfg b/board/freescale/t208xrdb/t2080_rcw.cfg
index 15e1bf4..700629a 100644
--- a/board/freescale/t208xrdb/t2080_rcw.cfg
+++ b/board/freescale/t208xrdb/t2080_rcw.cfg
@@ -1,8 +1,9 @@
-#PBL preamble and RCW header for T2080RDB
+#For T2080 silicon v1.1 on RDB board
+#PBL preamble and RCW header
 aa55aa55 010e0100
-#SerDes Protocol: 0x66_0x16
-#Core/DDR: 1533Mhz/1600MT/s
-120c0017 15000000 00000000 00000000
-66150002 00008400 ec104000 c1000000
-00000000 00000000 00000000 000307fc
+#SerDes Protocol: 0x66_0x15
+#Core:1800MHz, DDR:1600MT/s
+1206001b 15000000 00000000 00000000
+66150002 00000000 e8104000 c1000000
+00800000 00000000 00000000 000307fc
 00000000 00000000 00000000 00000004
-- 
1.8.0