[U-Boot] [PATCH 2/3] B4860QDS: SGMII related updates
Shaveta Leekha
shaveta at freescale.com
Wed Nov 12 11:10:51 CET 2014
- Enable SGMII support for 0x8d Serdes 2 protocol.
- Correct Phy address for DTSECx for 0x8d/0xb2 Serdes 2 protocol.
- Updated debug statement
- Add Alternate LC VCO protocols(0x8d-->0x8c, 0xb2-->0xb1)
- Rename onboard PHY address defines for more readability
- Add these new Defines in B4860QDS.h file
Signed-off-by: Shaveta Leekha <shaveta at freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal at freescale.com>
Signed-off-by: Suresh Gupta <suresh.gupta at freescale.com>
Change-Id: I4d9a8c602bdaac8404577ab9642f8c5f37ac7cdc
Reviewed-on: http://git.am.freescale.net:8181/23353
Tested-by: Review Code-CDREVIEW <CDREVIEW at freescale.com>
Reviewed-by: Yusong Sun <yorksun at freescale.com>
---
board/freescale/b4860qds/eth_b4860qds.c | 64 ++++++++++++++++++------------
include/configs/B4860QDS.h | 4 +-
2 files changed, 40 insertions(+), 28 deletions(-)
diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c
index 12df9a8..2726cd2 100644
--- a/board/freescale/b4860qds/eth_b4860qds.c
+++ b/board/freescale/b4860qds/eth_b4860qds.c
@@ -112,7 +112,10 @@ static void initialize_lane_to_slot(void)
* Lanes: A,B,C,D: PCI
* Lanes: E,F,G,H: XAUI2
*/
+ case 0xb1:
case 0xb2:
+ case 0x8c:
+ case 0x8d:
/*
* Configuration:
* SERDES: 2
@@ -195,34 +198,34 @@ int board_eth_init(bd_t *bis)
* all SGMII. RGMII is not supported on this board. Setting SGMII 5 and
* 6 to on board SGMII phys
*/
- fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
switch (serdes1_prtcl) {
case 0x29:
case 0x2a:
/* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */
- debug("Setting phy addresses for FM1_DTSEC5: %x and"
- "FM1_DTSEC6: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR,
- CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+ debug("Set phy addresses for FM1_DTSEC5:%x, FM1_DTSEC6:%x\n",
+ CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR,
+ CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
fm_info_set_phy_address(FM1_DTSEC5,
- CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
+ CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
fm_info_set_phy_address(FM1_DTSEC6,
- CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+ CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
break;
#ifdef CONFIG_PPC_B4420
case 0x17:
case 0x18:
/* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */
- debug("Setting phy addresses for FM1_DTSEC3: %x and"
- "FM1_DTSEC4: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR,
- CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+ debug("Set phy addresses for FM1_DTSEC3:%x, FM1_DTSEC4:%x\n",
+ CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR,
+ CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
/* Fixing Serdes clock by programming FPGA register */
QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
fm_info_set_phy_address(FM1_DTSEC3,
- CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
+ CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
fm_info_set_phy_address(FM1_DTSEC4,
- CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+ CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
break;
#endif
default:
@@ -233,8 +236,8 @@ int board_eth_init(bd_t *bis)
switch (serdes2_prtcl) {
case 0x17:
case 0x18:
- debug("Setting phy addresses on SGMII Riser card for"
- "FM1_DTSEC ports: \n");
+ debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n",
+ CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC1,
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2,
@@ -246,8 +249,8 @@ int board_eth_init(bd_t *bis)
break;
case 0x48:
case 0x49:
- debug("Setting phy addresses on SGMII Riser card for"
- "FM1_DTSEC ports: \n");
+ debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n",
+ CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC1,
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2,
@@ -255,10 +258,12 @@ int board_eth_init(bd_t *bis)
fm_info_set_phy_address(FM1_DTSEC3,
CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR);
break;
- case 0x8d:
+ case 0xb1:
case 0xb2:
- debug("Setting phy addresses on SGMII Riser card for"
- "FM1_DTSEC ports: \n");
+ case 0x8c:
+ case 0x8d:
+ debug("Set phy addresses on SGMII Riser for FM1_DTSEC1:%x\n",
+ CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC3,
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC4,
@@ -266,18 +271,18 @@ int board_eth_init(bd_t *bis)
break;
case 0x98:
/* XAUI in Slot1 and Slot2 */
- debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC1: %x\n",
+ debug("Set phy address of AMC2PEX-2S for FM1_10GEC1:%x\n",
CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
fm_info_set_phy_address(FM1_10GEC1,
CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
- debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC2: %x\n",
+ debug("Set phy address of AMC2PEX-2S for FM1_10GEC2:%x\n",
CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
fm_info_set_phy_address(FM1_10GEC2,
CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
break;
case 0x9E:
/* XAUI in Slot2 */
- debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC2: %x\n",
+ debug("Sett phy address of AMC2PEX-2S for FM1_10GEC2:%x\n",
CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
fm_info_set_phy_address(FM1_10GEC2,
CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
@@ -329,17 +334,20 @@ int board_eth_init(bd_t *bis)
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
fm_info_set_mdio(i,
- miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME));
+ miiphy_get_dev_by_name
+ (DEFAULT_FM_TGEC_MDIO_NAME));
+ break;
+ case PHY_INTERFACE_MODE_NONE:
+ fm_info_set_phy_address(i, 0);
break;
default:
- printf("Fman1: 10GSEC%u set to unknown interface %i\n",
+ printf("Fman1: TGEC%u set to unknown interface %i\n",
idx + 1, fm_info_get_enet_if(i));
fm_info_set_phy_address(i, 0);
break;
}
}
-
cpu_eth_init(bis);
#endif
@@ -357,15 +365,19 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
sprintf(alias, "phy_sgmii_%x", phy);
fdt_set_phy_handle(fdt, compat, addr, alias);
+ fdt_status_okay_by_alias(fdt, alias);
}
}
+/*
+ * Set status to disabled for unused ethernet node
+ */
void fdt_fixup_board_enet(void *fdt)
{
int i;
char alias[32];
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ for (i = FM1_DTSEC1; i <= FM1_10GEC2; i++) {
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_NONE:
sprintf(alias, "ethernet%u", i);
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index dc1a9bc..b47b9de 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -713,8 +713,8 @@ unsigned long get_board_ddr_clk(void);
#endif /* CONFIG_PCI */
#ifdef CONFIG_FMAN_ENET
-#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10
-#define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11
+#define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
+#define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
/*B4860 QDS AMC2PEX-2S default PHY_ADDR */
#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/
--
1.7.6.GIT
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