[U-Boot] iMX6 DDR Calibration Value

[Fabio Estevam]

On Thu, Nov 13, 2014 at 11:19 PM, John Tobias <john.tobias.ph at gmail.com> wrote:
> Hi Fabio / Stefano,
>
> May be you could help me to get some answer regarding with
> calibrations value for DDR.
>
> I have a 4 custom boards based on iMX6SL (2) Micron DDR and (2) Samsung DDR.
>
> The boards has exact DDR footprints (like density, bus width and so
> on). In fact the uboot that I am using works on both DDR chips.
>
> I re-ran the DDR tools twice for each boards, entered the same
> information. The tools returned different calibration values for each
> boards but, the two results for each boards were the same.
>
>
> e.g: board1
>
> Read DQS Gating calibration
> MPDGCTRL0 PHY0 (0x021b083c) = 0x412C0130
> MPDGCTRL1 PHY0 (0x021b0840) = 0x01140118
>
> Read calibration
> MPRDDLCTL PHY0 (0x021b0848) = 0x3E404244
>
> Write calibration
> MPWRDLCTL PHY0 (0x021b0850) = 0x383C3E36
>
> board2:
>
>  Read DQS Gating calibration
>  MPDGCTRL0 PHY0 (0x021b083c) = 0x412C0130
>  MPDGCTRL1 PHY0 (0x021b0840) = 0x01140118
>
>  Read calibration
>  MPRDDLCTL PHY0 (0x021b0848) = 0x3E3E4244
>
>  Write calibration
>  MPWRDLCTL PHY0 (0x021b0850) = 0x383C3E36
>
> Is there any procedures or rules of thumb you follow dealing with the
> calibration settings?.

Then you need to provide a mx6_mmdc_calibration structure for each board, right?

Take a look at gw_ventana_spl.c for an example on how this is done.

Regards,

Fabio Estevam