[U-Boot] [PATCH v2 0/30] x86: Add additional system setup for ivybridge

Simon Glass sjg at chromium.org
Sat Nov 15 02:18:18 CET 2014


This series adds full support for the LPC (Low Pin Count) bridge, the
PCH (Platform Controller Hub), PCI devices like USB and SATA and more
CPU init support (turbo mode, etc.)

With this series, chromebook_link can use SATA and USB at the command
line.

Changes in v2:
- Adjust rtc_init() call to remove the parameter
- Change 'not' to 'no' since it reads better
- Drop WIP commit for u-boot.srec as it is not needed now
- Drop the part of the commit message that talks about using build date
- Fix 'AT' value in link script
- Move CLEAR_CMOS up to the top, indicated to be manually changed
- Move common SATA init to a function to reduce duplication
- Remove ISA DMA init which isn't needed in U-Boot
- Remove i8259 patch and just update the existing interrupt code
- Remove the parameter from rtc_init() and simplify the code
- Remove use of __PRE_RAM__ define
- Rename functions to pci_read_bar32() and pci_write_bar32()
- Use .rel* instead of .rel.* to catch more cases
- Use existing lapic_setup() code instead of duplicating it
- Use i8259 init in pcat_interrupts.c
- Use interrupt.h header instead of i8259.h
- Use pci_write_bar32() to write to BARs

Simon Glass (30):
  Align embedded device tree correctly
  Add ALIGN_DOWN() to find next smallest alignment
  pci: Update pci_ids.h to include some missing IDs
  x86: Remove board_early_init_r()
  x86: Panic if there is no relocation data
  x86: Ensure that all relocation data is included in the image
  x86: Factor out common values in the link script
  rtc: mc146818: Set up RTC at start of day
  x86: Add ioapic.h header
  x86: pci: Add handlers before and after a PCI hose scan
  x86: config: Enable plug-and-play for link PCI
  pci: Add functions to read and write a BAR address
  x86: Set up edge triggering on interrupt 9
  x86: ivybridge: Add support for BD82x6x PCH
  x86: Add a simple header file for ACPI
  x86: ivybridge: Add PCH init
  x86: ivybridge: Add additional LPC init
  x86: dts: Move PCI peripherals into a pci node
  x86: dts: Add LPC settings for link
  x86: ivybridge: Add SATA init
  x86: dts: Add SATA settings for link
  x86: ivybridge: Set up EHCI USB
  x86: config: Enable USB on link
  x86: ivybridge: Set up XHCI USB
  x86: Add Intel speedstep and turbo mode code
  x86: Add LAPIC setup code
  x86: Add init for model 206AX CPU
  x86: Drop some msr functions that we don't support
  x86: ivybridge: Add northbridge init functions
  x86: config: Enable SPI for chromebook_link

 arch/x86/cpu/Makefile                             |   2 +
 arch/x86/cpu/config.mk                            |   5 +-
 arch/x86/cpu/coreboot/coreboot.c                  |  11 -
 arch/x86/cpu/ivybridge/Makefile                   |   7 +
 arch/x86/cpu/ivybridge/bd82x6x.c                  | 135 ++++++
 arch/x86/cpu/ivybridge/lpc.c                      | 523 +++++++++++++++++++++-
 arch/x86/cpu/ivybridge/model_206ax.c              | 514 +++++++++++++++++++++
 arch/x86/cpu/ivybridge/northbridge.c              | 188 ++++++++
 arch/x86/cpu/ivybridge/pch.c                      | 123 +++++
 arch/x86/cpu/ivybridge/pci.c                      |  40 ++
 arch/x86/cpu/ivybridge/sata.c                     | 225 ++++++++++
 arch/x86/cpu/ivybridge/usb_ehci.c                 |  29 ++
 arch/x86/cpu/ivybridge/usb_xhci.c                 |  32 ++
 arch/x86/cpu/lapic.c                              |  62 +++
 arch/x86/cpu/pci.c                                |  12 +
 arch/x86/cpu/turbo.c                              |  98 ++++
 arch/x86/cpu/u-boot.lds                           |  18 +-
 arch/x86/dts/link.dts                             |  41 +-
 arch/x86/include/asm/acpi.h                       |  24 +
 arch/x86/include/asm/arch-ivybridge/bd82x6x.h     |  21 +
 arch/x86/include/asm/arch-ivybridge/model_206ax.h |   4 +
 arch/x86/include/asm/arch-ivybridge/pch.h         | 120 +++++
 arch/x86/include/asm/arch-ivybridge/sandybridge.h |  13 +-
 arch/x86/include/asm/interrupt.h                  |  11 +
 arch/x86/include/asm/ioapic.h                     |  38 ++
 arch/x86/include/asm/lapic.h                      | 125 +++++-
 arch/x86/include/asm/msr-index.h                  |   2 +
 arch/x86/include/asm/msr.h                        |  11 -
 arch/x86/include/asm/pci.h                        |   3 +
 arch/x86/include/asm/post.h                       |   1 +
 arch/x86/include/asm/speedstep.h                  |  89 ++++
 arch/x86/include/asm/turbo.h                      |  31 ++
 arch/x86/lib/pcat_interrupts.c                    |  38 ++
 arch/x86/lib/relocate.c                           |   3 +
 board/google/chromebook_link/link.c               |   5 -
 common/board_r.c                                  |   3 -
 doc/device-tree-bindings/ata/intel-sata.txt       |  26 ++
 doc/device-tree-bindings/misc/intel-lpc.txt       |  47 +-
 drivers/pci/pci.c                                 |  24 +-
 drivers/rtc/mc146818.c                            |  43 +-
 include/common.h                                  |  15 +
 include/configs/chromebook_link.h                 |  11 +-
 include/fdtdec.h                                  |   2 +
 include/pci.h                                     |  23 +
 include/pci_ids.h                                 | 187 +++++++-
 include/rtc.h                                     |   5 +
 lib/fdtdec.c                                      |   2 +
 scripts/Makefile.lib                              |   2 +
 48 files changed, 2915 insertions(+), 79 deletions(-)
 create mode 100644 arch/x86/cpu/ivybridge/bd82x6x.c
 create mode 100644 arch/x86/cpu/ivybridge/model_206ax.c
 create mode 100644 arch/x86/cpu/ivybridge/northbridge.c
 create mode 100644 arch/x86/cpu/ivybridge/pch.c
 create mode 100644 arch/x86/cpu/ivybridge/sata.c
 create mode 100644 arch/x86/cpu/ivybridge/usb_ehci.c
 create mode 100644 arch/x86/cpu/ivybridge/usb_xhci.c
 create mode 100644 arch/x86/cpu/lapic.c
 create mode 100644 arch/x86/cpu/turbo.c
 create mode 100644 arch/x86/include/asm/acpi.h
 create mode 100644 arch/x86/include/asm/arch-ivybridge/bd82x6x.h
 create mode 100644 arch/x86/include/asm/ioapic.h
 create mode 100644 arch/x86/include/asm/speedstep.h
 create mode 100644 arch/x86/include/asm/turbo.h
 create mode 100644 doc/device-tree-bindings/ata/intel-sata.txt

-- 
2.1.0.rc2.206.gedb03e5



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