[U-Boot] [PATCH] driver/ddr/fsl: Fix tMOD calculation for DDR3

[York Sun]

JEDEC specifies tMOD = max(12nCK, 15ns) for DDR3. This value
is used in mode register set cycle time.

Signed-off-by: York Sun <yorksun at freescale.com>
---
 drivers/ddr/fsl/ctrl_regs.c |    7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 9a156bf..6fa7165 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -327,7 +327,12 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
 	 */
 	txp = max(mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000));
 
-	tmrd_mclk = 4;
+	/*
+	 * MRS_CYC = max(tMRD, tMOD)
+	 * tMRD = 4nCK, tMOD = max(12nCK, 15ns)
+	 */
+	tmrd_mclk = max(12, picos_to_mclk(15000));
+
 	/* set the turnaround time */
 
 	/*
-- 
1.7.9.5