[U-Boot] [PATCH] mpc85xx/sleep: flush cache after restoring DDR data

[b29983 at freescale.com]

From: Tang Yuantian <Yuantian.Tang at freescale.com>

Cache needs to be flushed after restoring DDR data.

Signed-off-by: Tang Yuantian <Yuantian.Tang at freescale.com>
---
 board/freescale/t102xrdb/t102xrdb.c | 2 ++
 board/freescale/t104xrdb/t104xrdb.c | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c
index c224b2b..69e9331 100644
--- a/board/freescale/t102xrdb/t102xrdb.c
+++ b/board/freescale/t102xrdb/t102xrdb.c
@@ -187,6 +187,8 @@ void fsl_dp_ddr_restore(void)
 	dst = (u64 *)CONFIG_SYS_SDRAM_BASE;
 	for (i = 0; i < DDR_BUFF_LEN / 8; i++)
 		*dst++ = *src++;
+
+	flush_dcache();
 }
 
 int fsl_dp_resume(void)
diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c
index ea0cac7..58ba649 100644
--- a/board/freescale/t104xrdb/t104xrdb.c
+++ b/board/freescale/t104xrdb/t104xrdb.c
@@ -144,6 +144,8 @@ void fsl_dp_ddr_restore(void)
 
 	for (i = 0; i < DDR_BUFF_LEN / 8; i++)
 		*dst++ = *src++;
+
+	flush_dcache();
 }
 
 int fsl_dp_resume(void)
-- 
2.1.0.27.g96db324