[U-Boot] [PATCH v3 25/26] x86: ivybridge: Implement SDRAM init
Simon Glass
sjg at chromium.org
Fri Nov 21 07:52:34 CET 2014
On 13 November 2014 06:42, Simon Glass <sjg at chromium.org> wrote:
> Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in
> the board directory and the SDRAM SPD information in the device tree. This
> also needs the Intel Management Engine (me.bin) to work. Binary blobs
> everywhere: so far we have MRC, ME and microcode.
>
> SDRAM init works by setting up various parameters and calling the MRC. This
> in turn does some sort of magic to work out how much memory there is and
> the timing parameters to use. It also sets up the DRAM controllers. When
> the MRC returns, we use the information it provides to map out the
> available memory in U-Boot.
>
> U-Boot normally moves itself to the top of RAM. On x86 the RAM is not
> generally contiguous, and anyway some RAM may be above 4GB which doesn't
> work in 32-bit mode. So we relocate to the top of the largest block of
> RAM we can find below 4GB. Memory above 4GB is accessible with special
> functions (see physmem).
>
> It would be possible to build U-Boot in 64-bit mode but this wouldn't
> necessarily provide any more memory, since the largest block is often below
> 4GB. Anyway U-Boot doesn't need huge amounts of memory - even a very large
> ramdisk seldom exceeds 100-200MB. U-Boot has support for booting 64-bit
> kernels directly so this does not pose a limitation in that area. Also there
> are probably parts of U-Boot that will not work correctly in 64-bit mode.
> The MRC is one.
>
> There is some work remaining in this area. Since memory init is very slow
> (over 500ms) it is possible to save the parameters in SPI flash to speed it
> up next time. Suspend/resume support is not fully implemented, or at least
> it is not efficient.
>
> With this patch, link boots to a prompt.
>
> Signed-off-by: Simon Glass <sjg at chromium.org>
> ---
>
> Changes in v3:
> - Add a CONFIG_X86_RAMTEST option to enable the SDRAM test
> - Rebase against x86/master
> - Use cpu_get_name() in report_paltform.c
> - Use the CONFIG_HAVE_INTEL_ME option in the Makefile
>
> Changes in v2:
> - Add mrc.bin dependency for u-boot.rom build rule
> - Adjust to use asm/cpu.h header for cpuid
> - Drop patch to move coreboot PCI into common cpu area
> - Drop patch which removes the early_board_init() feature
> - Fix incorrect subl mnemonic in start.S
> - Remove use of PCI_CPU_DEVICE and use PCH_DEV instead
>
> arch/x86/Kconfig | 20 +
> arch/x86/cpu/ivybridge/Kconfig | 1 +
> arch/x86/cpu/ivybridge/Makefile | 3 +
> arch/x86/cpu/ivybridge/early_me.c | 191 ++++++++
> arch/x86/cpu/ivybridge/me_status.c | 195 ++++++++
> arch/x86/cpu/ivybridge/report_platform.c | 89 ++++
> arch/x86/cpu/ivybridge/sdram.c | 553 +++++++++++++++++++++-
> arch/x86/cpu/start.S | 10 +-
> arch/x86/dts/link.dts | 111 +++++
> arch/x86/include/asm/arch-ivybridge/me.h | 356 ++++++++++++++
> arch/x86/include/asm/arch-ivybridge/pch.h | 113 +++++
> arch/x86/include/asm/arch-ivybridge/pei_data.h | 121 +++++
> arch/x86/include/asm/arch-ivybridge/sandybridge.h | 2 +
> arch/x86/include/asm/config.h | 1 +
> arch/x86/include/asm/global_data.h | 13 +
> arch/x86/include/asm/post.h | 5 +
> arch/x86/include/asm/u-boot-x86.h | 2 +
> arch/x86/lib/Makefile | 1 +
> arch/x86/lib/ramtest.c | 79 ++++
> include/configs/chromebook_link.h | 4 +
> include/configs/x86-common.h | 2 +-
> include/fdtdec.h | 1 +
> lib/fdtdec.c | 1 +
> 23 files changed, 1868 insertions(+), 6 deletions(-)
> create mode 100644 arch/x86/cpu/ivybridge/early_me.c
> create mode 100644 arch/x86/cpu/ivybridge/me_status.c
> create mode 100644 arch/x86/cpu/ivybridge/report_platform.c
> create mode 100644 arch/x86/include/asm/arch-ivybridge/me.h
> create mode 100644 arch/x86/include/asm/arch-ivybridge/pei_data.h
> create mode 100644 arch/x86/lib/ramtest.c
Applied to u-boot-x86.
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