[U-Boot] [PATCH v9 1/2] Odroid-XU3: Add support for Odroid-XU3

[Hyungwon Hwang]

On Thu, 27 Nov 2014 22:45:18 +0100
Sjoerd Simons <sjoerd.simons at collabora.co.uk> wrote:

> On Thu, 2014-11-27 at 22:21 +0900, Hyungwon Hwang wrote:
> > This patch adds support for Odroid-XU3.
> 
> I can't seem to access the EMMC with this patch, is that expected?
> 

Yes. EMMC is not supported yet. Actually even I did not test whether it
works or not. EMMC support will be done soon.

> 
> > --- /dev/null
> > +++ b/board/samsung/odroid-xu3/Kconfig
> > @@ -0,0 +1,12 @@
> > +if TARGET_ODROID_XU3
> > +
> > +config SYS_BOARD
> > +	default "odroid-xu3"
> > +
> > +config SYS_VENDOR
> > +	default "samsung"
> > +
> > +config SYS_CONFIG_NAME
> > +	default "odroid_xu3"
> > +
> > +endif
> 
> I was studying the different between the peach-pi and the XU3 hardware
> enablement a bit. I was wondering whta's the rationale for the XU3
> having it's own board file and reconfiguring various clocks? Does the
> hardkernel SPL/bl2 not setup things correctly?
> 

Hmm. It is my first time to make codes to add support for new board, and
I am not sure what is right. Is it needless to set clocks for the cases
when SPL/BL2 is expected to set clocks already?

> > diff --git a/board/samsung/odroid-xu3/odroid-xu3.c
> > b/board/samsung/odroid-xu3/odroid-xu3.c new file mode 100644
> > index 0000000..8c54842
> > --- /dev/null
> > +++ b/board/samsung/odroid-xu3/odroid-xu3.c
> > @@ -0,0 +1,122 @@
> > +/*
> > + * Copyright (C) 2014 Samsung Electronics
> > + * Hyungwon Hwang <human.hwang at samsung.com>
> > + *
> > + * SPDX-License-Identifier:	GPL-2.0+
> > + */
> > +
> > +#include <common.h>
> > +#include <asm/arch/clock.h>
> > +#include "setup.h"
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +unsigned int get_board_rev(void)
> > +{
> > +	return 0;
> > +}
> > +
> > +int exynos_init(void)
> > +{
> > +	return 0;
> > +}
> > +
> > +#ifdef CONFIG_BOARD_EARLY_INIT_F
> > +static int board_clock_init(void)
> > +{
> > +	unsigned int set, clr, clr_src_cpu, clr_pll_con0;
> > +	struct exynos5420_clock *clk = (struct exynos5420_clock *)
> > +
> > samsung_get_base_clock();
> > +	/*
> > +	 * CMU_CPU clocks src to MPLL
> > +	 * Bit values:                 0  ; 1
> > +	 * MUX_APLL_SEL:        FIN_PLL   ; FOUT_APLL
> > +	 * MUX_CORE_SEL:        MOUT_APLL ; SCLK_MPLL
> > +	 * MUX_HPM_SEL:         MOUT_APLL ; SCLK_MPLL_USER_C
> > +	 * MUX_MPLL_USER_SEL_C: FIN_PLL   ; SCLK_MPLL
> > +	*/
> > +
> > +	/* Set CMU_CPU clocks src to OSCCLK */
> > +	clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1);
> > +	set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1);
> > +
> > +	clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
> > +
> > +	while (MUX_STAT_CPU_CHANGING(readl(&clk->mux_stat_cpu)))
> > +		continue;
> > +
> > +	/* Set APLL to 1200MHz */
> > +	clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1) |
> > +			PLL_ENABLE(1);
> > +	set = SDIV(0) | PDIV(2) | MDIV(100) | PLL_ENABLE(1);
> > +
> > +	clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set);
> > +
> > +	while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT))
> > +		continue;
> > +
> > +	/* Set CMU_CPU clocks src to APLL */
> > +	set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0);
> > +	clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
> > +
> > +	while (MUX_STAT_CPU_CHANGING(readl(&clk->mux_stat_cpu)))
> > +		continue;
> > +
> > +	clr = ARM_RATIO(7) | CPUD_RATIO(7) | ATB_RATIO(7) |
> > +	      PCLK_DBG_RATIO(7) | APLL_RATIO(7) | ARM2_RATIO(7);
> > +	set = ARM_RATIO(0) | CPUD_RATIO(2) | ATB_RATIO(5) |
> > +	      PCLK_DBG_RATIO(5) | APLL_RATIO(0) | ARM2_RATIO(0);
> > +
> > +	clrsetbits_le32(&clk->div_cpu0, clr, set);
> > +
> > +	while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING)
> > +		continue;
> > +
> > +	/* Set MPLL to 800MHz */
> > +	set = SDIV(1) | PDIV(3) | MDIV(200) | PLL_ENABLE(1);
> > +
> > +	clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set);
> > +
> > +	while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT))
> > +		continue;
> > +
> > +	/* Set CLKMUX_UART src to MPLL */
> > +	clr = UART0_SEL(7) | UART1_SEL(7) | UART2_SEL(7) |
> > UART3_SEL(7);
> > +	set = UART0_SEL(3) | UART1_SEL(3) | UART2_SEL(3) |
> > UART3_SEL(3); +
> > +	clrsetbits_le32(&clk->src_peric0, clr, set);
> > +
> > +	/* Set SCLK_UART to 400 MHz (MPLL / 2) */
> > +	clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) |
> > +	      UART3_RATIO(15);
> > +	set = UART0_RATIO(1) | UART1_RATIO(1) | UART2_RATIO(1) |
> > +	      UART3_RATIO(1);
> > +
> > +	clrsetbits_le32(&clk->div_peric0, clr, set);
> > +
> > +	while (readl(&clk->div_stat_peric0) &
> > DIV_STAT_PERIC0_CHANGING)
> > +		continue;
> > +
> > +	/* Set CLKMUX_MMC src to MPLL */
> > +	clr = MUX_MMC0_SEL(7) | MUX_MMC1_SEL(7) | MUX_MMC2_SEL(7);
> > +	set = MUX_MMC0_SEL(3) | MUX_MMC1_SEL(3) | MUX_MMC2_SEL(3);
> > +
> > +	clrsetbits_le32(&clk->src_fsys, clr, set);
> > +
> > +	clr = MMC0_RATIO(0x3ff) | MMC1_RATIO(0x3ff) |
> > MMC2_RATIO(0x3ff);
> > +	set = MMC0_RATIO(0) | MMC1_RATIO(0) | MMC2_RATIO(0);
> > +
> > +	clrsetbits_le32(&clk->div_fsys1, clr, set);
> > +
> > +	/* Wait for divider ready status */
> > +	while (readl(&clk->div_stat_fsys1) &
> > DIV_STAT_FSYS1_CHANGING)
> > +		continue;
> > +
> > +	return 0;
> > +}
> > +
> > +int exynos_early_init_f(void)
> > +{
> > +	return board_clock_init();
> > +}
> > +#endif
> 
>