[U-Boot] Commit 294b91a5817147d4b7f47be2ac69bac2a1f26491 broke mpc85xx

[Scott Wood]

On Wed, 2014-10-01 at 09:27 -0700, York Sun wrote:
> On 10/01/2014 08:11 AM, Simon Glass wrote:
> > Hi York,
> > 
> > 
> > On 30 September 2014 22:06, York Sun <yorksun at freescale.com> wrote:
> >> Simon,
> >>
> >> I didn't notice until today the commit
> >> 294b91a5817147d4b7f47be2ac69bac2a1f26491 broke at least T4240QDS. I have
> >> narrowed down to these two lines in common/board_r.c
> >>
> >> initr_barrier,
> >>         initr_malloc,
> >>
> >> If I move these two lines below this part
> >>
> >>
> >> #if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500)
> >>         initr_unlock_ram_in_cache,
> >> #endif
> >>
> >>
> >> U-boot boots OK on T4240QDS (I can see the prompt). But if I move them
> >> anywhere above this initr_unlock_ram_in_cache, it hangs the core when
> >> initializing PCI. It may break other mpc85xx platforms but I didn't have
> >> time to check more today. I haven't figured out why you have to move these
> >> two lines up. Please take a close look.
> > 
> > I could adjust this so that the ordering changes only when driver model is used.
> > 
> > This would be a case of putting '#ifdef CONFIG_DM' around the first
> > section, then repeating it later with '#ifndef CONFIG_DM'. You can see
> > that I did this for stdio out of an abundance of caution.
> > 
> > However, in the interests of supporting driver model on these
> > platforms I wonder if it might be possible to move the cache logic
> > earlier. I suspect that the unlock/invalidate should happen before
> > post-relocation RAM is used.
> > 
> > Please take a look and let me know if that might be possible.
> > Otherwise we'll have to go with the fallback.
> 
> I can change init sequence as far as I put initr_unlock_ram_in_cache before
> initr_malloc, T4240QDS still boots.

Yes, we shouldn't have any reason to keep the cache locked that long.

> I examine the code but don't understand why I have to do so. P4080DS doesn't
> suffer this issue. I am going to seek some help from Scott and other in-house
> experts.

My guess is that it has to do with the way caches work on e6500.  We try
to lock lines in L1, but L1 can't hold dirty lines, so perhaps the hang
comes when the DDR activity evicts the dirty lines from L2 (where they
weren't locked).

-Scott