[U-Boot] [PATCH v3 08/10] ARM: sun6i: Setup the A31 UART0 muxing

[Chen-Yu Tsai]

From: Maxime Ripard <maxime.ripard at free-electrons.com>

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
Signed-off-by: Hans de Goede <hdegoede at redhat.com>
[wens at csie.org: commit message was "ARM: sunxi: Setup the A31 UART0 muxing"]
[wens at csie.org: reorder #ifs by SUN?I]
[wens at csie.org: replace magic numbers with GPIO definitions]
Signed-off-by: Chen-Yu Tsai <wens at csie.org>
Acked-by: Ian Campbell <ijc at hellion.org.uk>
---
 arch/arm/cpu/armv7/sunxi/board.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 95a74c5..b6d63db 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -58,6 +58,10 @@ int gpio_init(void)
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
 	sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN6I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH20_UART0_TX);
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH21_UART0_RX);
+	sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_SUN5I)
 	sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
 	sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
-- 
2.1.1