[U-Boot] [PATCH] cmd_sf: add handler for +len arg for all commands

[Maxime Hadjinlian]

On Sun, Oct 5, 2014 at 10:28 PM, Marek Vasut <marex at denx.de> wrote:
> On Sunday, October 05, 2014 at 09:51:27 PM, Maxime Hadjinlian wrote:
>> On Sun, Oct 5, 2014 at 9:45 PM, Marek Vasut <marex at denx.de> wrote:
>> > On Sunday, October 05, 2014 at 09:27:00 PM, Maxime Hadjinlian wrote:
>> >> On Sun, Oct 5, 2014 at 9:19 PM,  <thomas.langer at lantiq.com> wrote:
>> >> >> On Sunday, October 05, 2014 at 08:40:26 PM, Maxime Hadjinlian wrote:
>> >> >> > Hi Thomas, all,
>> >> >> >
>> >> >> > On Sun, Oct 5, 2014 at 7:43 PM,  <thomas.langer at lantiq.com> wrote:
>> >> >> > > Hello Maxime,
>> >> >> > >
>> >> >> > > can you explain the usecase?
>> >> >> > > I think, only the erase is executed per sector, all other
>> >> >> > > commands are working fine with a byte oriented length.
>> >> >> >
>> >> >> > I need to write a file that is downloaded through TFTP. So I can
>> >> >> > get the filesize through the variable of the same name, but if
>> >> >> > it's not rounded, the write command may fail.
>> >> >> > I can save the filesize in another variable, but at next boot, when
>> >> >> > I need to read this file, I can't read the file, since I only know
>> >> >> > it's size in byte, I need to be able to round it again.
>> >> >>
>> >> >> I wonder, do all SPI flashes need to do sector-aligned writes ?
>> >> >
>> >> > All the serial flashes I have seen so far do support reading and
>> >> > writing with any length, independent from the erase size.
>> >> > Otherwise the current implementation of env_sf.c would also not work.
>> >>
>> >> Well the QSPI, I used, does not. Every read and write has to be
>> >> aligned. That's why I needed that in the first place.
>> >
>> > Aligned how exactly?
>>
>> sector-aligned.
>> If I write anything that is not sector aligned, the 'sf' command will fail.
>
> Is that really a property of the SPI flash or the SPI controller ? And if the
> later, is it a property of a particular one or is that a common thing ?
I'll have to check but if I remember correctly, it's the SPI flash.
It's a Micron Serial NOR flash (N25Q512A83G1240x).
And the controller is the Cadence QSPI controller available on the SoC
FPGA platform.
Maybe what caused my issues was the driver after all ?
>
> Which SPI flash are you talking about and which controller ?
>
> Best regards,
> Marek Vasut