[U-Boot] [PATCH 05/10] mtd: nand: s3c: Add S3C2440 specifics
Marek Vasut
marex at denx.de
Sat Oct 11 18:42:53 CEST 2014
Add support for S3C2440 into the NAND driver by filling in the
S3C2440 bits and differences.
Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Kyungmin Park <kyungmin.park at samsung.com>
Cc: Lukasz Majewski <l.majewski at samsung.com>
Cc: Minkyu Kang <mk7.kang at samsung.com>
Cc: Scott Wood <scottwood at freescale.com>
Cc: Vladimir Zapolskiy <vz at mleia.com>
---
drivers/mtd/nand/s3c2410_nand.c | 55 ++++++++++++++++++++++++++++++++---------
1 file changed, 43 insertions(+), 12 deletions(-)
diff --git a/drivers/mtd/nand/s3c2410_nand.c b/drivers/mtd/nand/s3c2410_nand.c
index 8db432f..4971342 100644
--- a/drivers/mtd/nand/s3c2410_nand.c
+++ b/drivers/mtd/nand/s3c2410_nand.c
@@ -12,13 +12,22 @@
#include <asm/io.h>
#define S3C2410_NFCONF_EN (1<<15)
+#define S3C2440_NFCONT_EN (1<<0)
#define S3C2410_NFCONF_512BYTE (1<<14)
#define S3C2410_NFCONF_4STEP (1<<13)
#define S3C2410_NFCONF_INITECC (1<<12)
+#define S3C2440_NFCONT_INITECC (1<<4)
#define S3C2410_NFCONF_nFCE (1<<11)
+#define S3C2440_NFCONT_nFCE (1<<1)
+#ifdef CONFIG_S3C2410
#define S3C2410_NFCONF_TACLS(x) ((x)<<8)
#define S3C2410_NFCONF_TWRPH0(x) ((x)<<4)
#define S3C2410_NFCONF_TWRPH1(x) ((x)<<0)
+#else /* S3C2412, S3C2440 */
+#define S3C2410_NFCONF_TACLS(x) ((x)<<12)
+#define S3C2410_NFCONF_TWRPH0(x) ((x)<<8)
+#define S3C2410_NFCONF_TWRPH1(x) ((x)<<4)
+#endif
#define S3C2410_ADDR_NALE 4
#define S3C2410_ADDR_NCLE 8
@@ -42,25 +51,30 @@ static void s3c24x0_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *chip = mtd->priv;
struct s3c24x0_nand *nand = s3c24x0_get_base_nand();
+ uint32_t sel_reg, sel_bit;
debug("hwcontrol(): 0x%02x 0x%08x\n", cmd & 0xff, ctrl);
if (ctrl & NAND_CTRL_CHANGE) {
- ulong IO_ADDR_W = (ulong)nand;
+ chip->IO_ADDR_W = &nand->nfconf;
if (!(ctrl & NAND_CLE))
- IO_ADDR_W |= S3C2410_ADDR_NCLE;
+ chip->IO_ADDR_W = &nand->nfaddr;
if (!(ctrl & NAND_ALE))
- IO_ADDR_W |= S3C2410_ADDR_NALE;
+ chip->IO_ADDR_W = &nand->nfcmd;
- chip->IO_ADDR_W = (void *)IO_ADDR_W;
+#ifdef CONFIG_S3C2410
+ sel_reg = (uint32_t)&nand->nfconf;
+ sel_bit = S3C2410_NFCONF_nFCE;
+#else
+ sel_reg = (uint32_t)&nand->nfcont;
+ sel_bit = S3C2440_NFCONT_nFCE;
+#endif
if (ctrl & NAND_NCE)
- writel(readl(&nand->nfconf) & ~S3C2410_NFCONF_nFCE,
- &nand->nfconf);
+ clrbits_le32(sel_reg, sel_bit);
else
- writel(readl(&nand->nfconf) | S3C2410_NFCONF_nFCE,
- &nand->nfconf);
+ setbits_le32(sel_reg, sel_bit);
}
if (cmd != NAND_CMD_NONE)
@@ -79,16 +93,27 @@ void s3c24x0_nand_enable_hwecc(struct mtd_info *mtd, int mode)
{
struct s3c24x0_nand *nand = s3c24x0_get_base_nand();
debug("s3c24x0_nand_enable_hwecc(%p, %d)\n", mtd, mode);
- writel(readl(&nand->nfconf) | S3C2410_NFCONF_INITECC, &nand->nfconf);
+#ifdef CONFIG_S3C2410
+ setbits_le32(&nand->nfconf, S3C2410_NFCONF_INITECC);
+#else
+ setbits_le32(&nand->nfcont, S3C2440_NFCONT_INITECC);
+#endif
}
static int s3c24x0_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
u_char *ecc_code)
{
struct s3c24x0_nand *nand = s3c24x0_get_base_nand();
+#ifdef CONFIG_S3C2410
ecc_code[0] = readb(&nand->nfecc);
ecc_code[1] = readb(&nand->nfecc + 1);
ecc_code[2] = readb(&nand->nfecc + 2);
+#else
+ uint32_t ecc = readl(&nand->nfmecc0);
+ ecc_code[0] = ecc;
+ ecc_code[1] = ecc >> 8;
+ ecc_code[2] = ecc >> 16;
+#endif
debug("s3c24x0_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n",
mtd , ecc_code[0], ecc_code[1], ecc_code[2]);
@@ -110,14 +135,14 @@ static int s3c24x0_nand_correct_data(struct mtd_info *mtd, u_char *dat,
int board_nand_init(struct nand_chip *nand)
{
- u_int32_t cfg;
+ uint32_t cfg = 0;
u_int8_t tacls, twrph0, twrph1;
struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
struct s3c24x0_nand *nand_reg = s3c24x0_get_base_nand();
debug("board_nand_init()\n");
- writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon);
+ setbits_le32(&clk_power->clkcon, 1 << 4);
/* initialize hardware */
#if defined(CONFIG_S3C24XX_CUSTOM_NAND_TIMING)
@@ -130,12 +155,18 @@ int board_nand_init(struct nand_chip *nand)
twrph1 = 8;
#endif
- cfg = S3C2410_NFCONF_EN;
+#ifdef CONFIG_S3C2410
+ cfg |= S3C2410_NFCONF_EN;
+#endif
cfg |= S3C2410_NFCONF_TACLS(tacls - 1);
cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
writel(cfg, &nand_reg->nfconf);
+#ifndef CONFIG_S3C2410
+ writel(S3C2440_NFCONT_EN, &nand_reg->nfcont);
+#endif
+
/* initialize nand_chip data structure */
nand->IO_ADDR_R = (void *)&nand_reg->nfdata;
nand->IO_ADDR_W = (void *)&nand_reg->nfdata;
--
2.1.1
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