[U-Boot] [PATCH 2/2] sunxi: nand: Fix nand clk calculation

[Hans de Goede]

Before the u-boot dram cleanup u-boot would always set PLL5 factor m to
2 (reg value 1) and div p to 1, and get_cmu_clk in the nand code
would calculate the pll5p clk like this:

clk = 24 * factor_n * factor_k / div_p / factor_m;

aka:

clk = 24 * factor_n * factor_k / (div_p * factor_m);

This is wrong however, factor_m is not used to calculate pll5p, and div_p is
not a straight divider, but it divides by 2 ^ div_p. Since with the m == 2 and
p == 1 settings used before the dram cleanup, this happend to do the right
thing in the form of dividing by 2. But with the new dram code div_p is 0,
and then the old get_cmu_clk code fails with a divide by 0 error.

This commit fixes this, by changing the clk calculation to the correct form of:

clk = (24 * factor_n * factor_k) >> div_p;

Signed-off-by: Hans de Goede <hdegoede at redhat.com>
---
 drivers/block/sunxi_nand/nfd/nand_blk.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/block/sunxi_nand/nfd/nand_blk.c b/drivers/block/sunxi_nand/nfd/nand_blk.c
index a632453..2169301 100644
--- a/drivers/block/sunxi_nand/nfd/nand_blk.c
+++ b/drivers/block/sunxi_nand/nfd/nand_blk.c
@@ -1095,16 +1095,15 @@ __u32 get_cmu_clk(void)
 {
 	__u32 reg_val;
 	__u32 div_p, factor_n;
-	__u32 factor_k, factor_m;
+	__u32 factor_k;
 	__u32 clock;
 
 	reg_val  = *(volatile unsigned int *)(0xf1c20000 + 0x20);
 	div_p    = (reg_val >> 16) & 0x3;
 	factor_n = (reg_val >> 8) & 0x1f;
 	factor_k = ((reg_val >> 4) & 0x3) + 1;
-	factor_m = ((reg_val >> 0) & 0x3) + 1;
 
-	clock = 24 * factor_n * factor_k/div_p/factor_m;
+	clock = (24 * factor_n * factor_k) >> div_p;
 
 	return clock;
 }
-- 
2.1.0