[U-Boot] [U-boot] [Patch v4 3/6] keystone2: msmc: add MSMC cache coherency support for K2L SOC

[Ivan Khoronzhuk]

On 10/20/2014 06:13 PM, Tom Rini wrote:
> On Wed, Oct 15, 2014 at 02:55:29AM +0300, Ivan Khoronzhuk wrote:
>> From: Hao Zhang <hzhang at ti.com>
>>
>> This patch adds Keystone II Lamar (K2L) SoC specific definitions
>> to support MSMC cache coherency.
>>
>> Acked-by: Vitaly Andrianov <vitalya at ti.com>
>> Signed-off-by: Hao Zhang <hzhang at ti.com>
>> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk at ti.com>
>> ---
>>   arch/arm/cpu/armv7/keystone/init.c | 3 +++
>>   1 file changed, 3 insertions(+)
>>
>> diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/cpu/armv7/keystone/init.c
>> index a8f8aee..a0ecfa2 100644
>> --- a/arch/arm/cpu/armv7/keystone/init.c
>> +++ b/arch/arm/cpu/armv7/keystone/init.c
>> @@ -32,6 +32,9 @@ int arch_cpu_init(void)
>>   #ifdef CONFIG_SOC_K2E
>>   	msmc_share_all_segments(13); /* PCIE 1 */
>>   #endif
>> +#ifdef CONFIG_SOC_K2L
>> +	msmc_share_all_segments(14); /* PCIE 1 */
>> +#endif
>>   
>>   	/*
>>   	 * just initialise the COM2 port so that TI specific
> Where does 13/14 come from and can we just define what that means in a
> K2-foo specific header so we can always do
> msmc_share_all_segments(K2_MSMC_SEGMENTS_NR) or whatever?  Thanks!
>

Ok, I will update it.
But, currently, there is  newer version,
[U-boot] [Patch v5 0/6] keystone2: add k2l SoC and k2l_evm board support
https://www.mail-archive.com/u-boot@lists.denx.de/msg150245.html

-- 
Regards,
Ivan Khoronzhuk