[U-Boot] [U-boot] [Patch v6 3/6] keystone2: msmc: add MSMC cache coherency support for K2L SOC

[Ivan Khoronzhuk]

From: Hao Zhang <hzhang at ti.com>

This patch adds Keystone II Lamar (K2L) SoC specific definitions
to support MSMC cache coherency.

Acked-by: Vitaly Andrianov <vitalya at ti.com>
Signed-off-by: Hao Zhang <hzhang at ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk at ti.com>
---
 arch/arm/cpu/armv7/keystone/init.c                | 12 ++++++------
 arch/arm/include/asm/arch-keystone/hardware-k2e.h |  3 +++
 arch/arm/include/asm/arch-keystone/hardware-k2l.h |  3 +++
 arch/arm/include/asm/arch-keystone/hardware.h     | 10 +++++++---
 4 files changed, 19 insertions(+), 9 deletions(-)

diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/cpu/armv7/keystone/init.c
index a8f8aee..62081b7 100644
--- a/arch/arm/cpu/armv7/keystone/init.c
+++ b/arch/arm/cpu/armv7/keystone/init.c
@@ -25,12 +25,12 @@ int arch_cpu_init(void)
 	chip_configuration_unlock();
 	icache_enable();
 
-	msmc_share_all_segments(8);  /* TETRIS */
-	msmc_share_all_segments(9);  /* NETCP */
-	msmc_share_all_segments(10); /* QM PDSP */
-	msmc_share_all_segments(11); /* PCIE 0 */
-#ifdef CONFIG_SOC_K2E
-	msmc_share_all_segments(13); /* PCIE 1 */
+	msmc_share_all_segments(KS2_MSMC_SEGMENT_TETRIS);
+	msmc_share_all_segments(KS2_MSMC_SEGMENT_NETCP);
+	msmc_share_all_segments(KS2_MSMC_SEGMENT_QM_PDSP);
+	msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE0);
+#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
+	msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE1);
 #endif
 
 	/*
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2e.h b/arch/arm/include/asm/arch-keystone/hardware-k2e.h
index 62172a4..a70c184 100644
--- a/arch/arm/include/asm/arch-keystone/hardware-k2e.h
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2e.h
@@ -34,6 +34,9 @@
 #define KS2_LPSC_PCIE_1			27
 #define KS2_LPSC_XGE			50
 
+/* MSMC */
+#define KS2_MSMC_SEGMENT_PCIE1		13
+
 /* Chip Interrupt Controller */
 #define KS2_CIC2_DDR3_ECC_IRQ_NUM	-1	/* not defined in K2E */
 #define KS2_CIC2_DDR3_ECC_CHAN_NUM	-1	/* not defined in K2E */
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2l.h b/arch/arm/include/asm/arch-keystone/hardware-k2l.h
index 3402d0c..c1fa3af 100644
--- a/arch/arm/include/asm/arch-keystone/hardware-k2l.h
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2l.h
@@ -53,6 +53,9 @@
 #define KS2_LPSC_FFTC_B			49
 #define KS2_LPSC_IQN_AIL		50
 
+/* MSMC */
+#define KS2_MSMC_SEGMENT_PCIE1		14
+
 /* Chip Interrupt Controller */
 #define KS2_CIC2_DDR3_ECC_IRQ_NUM	0x0D3
 #define KS2_CIC2_DDR3_ECC_CHAN_NUM	0x01D
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h
index adae69e..295c6b0 100644
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -140,6 +140,13 @@ typedef volatile unsigned int   *dv_reg_p;
 /* Flag from ks2_debug options to check if DSPs need to stay ON */
 #define DBG_LEAVE_DSPS_ON		0x1
 
+/* MSMC control */
+#define KS2_MSMC_CTRL_BASE		0x0bc00000
+#define KS2_MSMC_SEGMENT_TETRIS		8
+#define KS2_MSMC_SEGMENT_NETCP		9
+#define KS2_MSMC_SEGMENT_QM_PDSP	10
+#define KS2_MSMC_SEGMENT_PCIE0		11
+
 /* Device speed */
 #define KS2_REV1_DEVSPEED		(KS2_DEVICE_STATE_CTRL_BASE + 0xc98)
 #define KS2_EFUSE_BOOTROM		(KS2_DEVICE_STATE_CTRL_BASE + 0xc90)
@@ -161,9 +168,6 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_QM_REGION_NUM		64
 #define KS2_QM_QPOOL_NUM		4000
 
-/* MSMC control */
-#define KS2_MSMC_CTRL_BASE		0x0bc00000
-
 /* USB */
 #define KS2_USB_SS_BASE			0x02680000
 #define KS2_USB_HOST_XHCI_BASE		(KS2_USB_SS_BASE + 0x10000)
-- 
1.8.3.2